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Features
* CPU32+ Processor (4.5 MIPS at 25 MHz)
- 32-bit Version of the CPU32 Core (Fully Compatible with the CPU32) - Background Debug Mode - Byte-misaligned Addressing Up to 32-bit Data Bus (Dynamic Bus Sizing for 8 and 16 Bits) Up to 32 Address Lines (At Least 28 Always Available) Complete Static Design (0 - 25 MHz Operation) Slave Mode to Disable CPU32+ (Allows Use with External Processors) - Multiple QUICCs Can Share One System Bus (One Master) - TS68040 Companion Mode Allows QUICC to be a TS68040 Companion Chip and Intelligent Peripheral (22 MIPS at 25 MHz) - Peripheral Device of TSPC603e (see DC415/D note) Four General-purpose Timers - Superset of MC68302 Timers - Four 16-bit Timers or Two 32-bit Timers - Gate Mode Can Enable/Disable Counting Two Independent DMAs (IDMAs) System Integration Module (SIM60) Communications Processor Module (CPM) Four Baud Rate Generators Four SCCs (Ethernet/IEEE 802.3 Optional on SCC1-Full 10 Mbps Support) Two SMC VCC = +5V 5% fmax = 25 MHz and 33 MHz Military Temperature Range: -55C < TC < +125C PD = 1.4 W at 25 MHz; 5.25V 2 W at 33 MHz; 5.25V
* * * *
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* * * * * * * * * *
32-bit Quad Integrated Communication Controller TS68EN360
Description
The TS68EN360 QUad Integrated Communication Controller (QUICCTM) is a versatile one-chip integrated microprocessor and peripheral combination that can be used in a variety of controller applications. It particularly excels in communications activities. The QUICC (pronounced "quick") can be described as a next-generation TS68302 with higher performance in all areas of device operation, increased flexibility, major extensions in capability, and higher integration. The term "quad" comes from the fact that there are four serial communications controllers (SCCs) on the device; however, there are actually seven serial channels: four SCCs, two serial management controllers (SMCs), and one serial peripheral interface (SPI).
Screening/Quality
This product is manufactured in full compliance with: * * * MIL-STD-883 (class B) QML (class Q) or according to Atmel standards
Rev. 2113A-HIREL-03/02
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R suffix PGA 241 Ceramic Pin Grid Array Cavity Up
A suffix CERQUAD 240 Ceramic Leaded Chip Carrier Cavity Down
Introduction
QUICC Architecture Overview
The QUICC is 32-bit controller that is an extension of other members of the TS68300 family. Like other members of the TS68300 family, the QUICC incorporates the intermodule bus (IMB). The TS68302 is an exception, having an 68000 bus on chip. The IMB provides a common interface for all modules of the TS68300 family, which allows the development of new devices more quickly by using the library of existing modules. Although the IMB definition always included an option for an on-chip 32-bit bus, the QUICC is the first device to implement this option. The QUICC is comprised of three modules: the CPU32+ core, the SIM60, and the CPM. Each module utilizes the 32-bit IMB. The TS68EN360 QUICC block diagram is shown in Figure 1. Figure 1. QUICC Block Diagram
SIM 60
SYSTEM PROTECTION CPU32+ CORE PERIODIC TIMER CLOCK GENERATION OTHER FEATURES JTAG
BREAKPOINT LOGIC
DRAM
CONTROLLER
AND
CHIP SELECTS
IMB (32 BIT)
EXTERNAL BUS INTERFACE
SYSTEM I/F
CPM
COMMUNICATIONS PROCESSOR RISC CONTROLLER TWO IDMAs FOURTEEN SERIAL DMAs SEVEN SERIAL CHANNELS 2.5-KBYTE DUAL-PORT RAM INTERRUPT CONTROLLER
FOUR GENERALPURPOSE TIMERS
TIMER SLOT ASSIGNER
OTHER FEATURES
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Pin Assignments
Figure 2. 241-lead Pin Grid Array (PGA)
T PA15 PA12 S D2 R D4 Q D7 P D10 N D13 M D16 L D19 K CLKO2 Vcc J CLKO1 D20 H D21 G D24 F D27 E D30 D FC2 C SIZ1 B SIZ0 A XTAL 1 2 NC4 3 A26 4 A24 5 A21 6 A18 7 A15 8 A12 9 A11 10 A9 11 A6 12 A3 13 A2 14 TRIS 15 CS6 16 CS3 17 CS0 18 A28 MODCK0 GND A25 A22 A19 A16 A13 A10 A7 A5 A1 IRQ7 CS5 CS2 CAS2 CAS1 A29 EXTAL MODCK1 A27 A23 A20 A17 A14 A8 A4 A0 CS7 CS4 CS1 CAS3 FREEZE DS FC1 A30 XFC Vcc GND GND Vcc Vcc GND GND GND GND Vcc GND CAS0 R/W DSACK0 FC3 FC0 A31 Vccsyn GNDsyn GND Vcc GNDs1 Vcc NC3 DSACK1 PRTY3 D29 D31 GND GND Vcc GND PRTY2 PRTY1 PRTY0 D26 D28 Vcc Vcc IPIPE0 AS IPIPE1 D23 D25 GND GNDs2 NC2 BCLRO OE D22 GND Vcc GND Vccclk GNDclk TS68EN360 (BOTTOM VIEW) GND GND IFETCH NC1 BR Vcc Vcc IRQ4 BGACK BG D18 D17 Vcc GND TRST BKPT IRQ6 D15 D14 GND Vcc TD1 TCK RESETH D12 D11 GND GND GND GND AVEC TDO TMS D9 D8 GND Vcc GND NC Vcc GND GND HALT RMC PERR D6 D5 GND GND GND Vcc Vcc GND GND Vcc Vcc GND GND GND IRQ5 BERR RESETS D3 D1 PA14 PA11 PA8 PA4 PA0 PB14 PB9 PB6 PB3 PB0 PC8 PC4 PC0 IRQ3 IRQ1 D0 PA13 PA10 PA7 PA5 PA1 PB16 PB13 PB10 PB7 PB4 PB1 PC10 PC7 PC3 PC1 IRQ2 PA9 PA6 PA3 PA2 PB17 PB15 PB12 PB11 PB8 PB5 PB2 PC11 PC9 PC6 PC5 PC2
Note:
Pin P9 "NC" is for guide purposes only.
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Figure 3. 240-lead Cerquad
CS0 CS1 CS2 CS3 Vcc GND CS4 CS5 CS6 CS7 IRQ7 TRIS A0 A1 GND A2 A3 Vcc A4 A5 GND A6 A7 Vcc GND A8 A9 GND A10 A11 Vcc A12 A13 GND A14 A15 A16 A17 A18 GND A19 A20 A21 Vcc A22 A23 A24 GND A25 A26 A27 NC4 GND MODCK1 MODCK0 XTAL EXTAL GNDsyn XFC Vccsyn GNDs1 CAS3 CAS2 Vcc CAS1 GND CAS0 FREEZE DS GND R/W NC3 Vcc DSACK0 GND DSACK1 GND PRTY3 PRTY2 GND Vcc PRTY1 PRTY0 IPIPE0 AS GNDs2 IPIPE1 Vcc NC2 BCLRO GND OE IFETCH NC1 BR Vcc GND BG BGACK Vcc IRQ4 IRQ6 GND BKPT RESETH TRST TCK TMS TDI TDO PERR GND AVEC RMC Vcc RESETS HALT GND BERR IRQ1 180 181 170 160 150 140 130 121 120
190 110
200 100
210
TS68EN360 (TOP VIEW) 90
220 80
230 70
PIN ONE INDICATOR
240 1 10 20 30 40 50 60
61
A28 A29 GND A30 A31 Vcc SIZ0 SIZ1 FC0 GND FC1 FC2 FC3 Vcc GND D31 D30 D29 GND D28 D27 D26 Vcc D25 D24 D23 GND D22 D21 D20 CLKO1 Vccclk GNDclk CLKO2 D19 D18 D17 GND D16 D15 Vcc D14 D13 D12 GND D11 D10 D9 D8 D7 GND D6 D5 Vcc D4 D3 D2 GND D1 D0
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IRQ5 IRQ3 IRQ2 PC0 PC1 PC2 GND PC3 PC4 PC5 PC6 Vcc PC7 PC8 PC9 PC10 GND PC11 PB0 PB1 PB2 PB3 PB4 PB5 PB6 GND PB7 PB8 PB9 PB10 Vcc PB11 PB12 PB13 PB14 GND PB15 PB16 PB17 PA0 GND Vcc PA1 PA2 PA3 PA4 GND PA5 PA6 PA7 PA8 Vcc PA9 PA10 PA11 PA12 GND PA13 PA14 PA15
TS68EN360
Signal Description
Functional Signal Group
Figure 4. QUICC Functional Signal Groups
ADDRESS BUS A27A0 A31A28/WE0WE3 FC2FC0/TM2TM0 FC3/TT0 PORT A RXD1/PA0 TXD1/PA1 RXD2/PA2 TXD2/PA3 L1TXDB/RXD3/PA4 L1RXDB/TXD3/PA5 L1TXDA/RXD4/PA6 L1RXDA/TXD4/PA7 TIMERs/SCCs/SIs/CLOCKs/BRG TIN1/L1RCLKA/BRGO1/CLK1/PA8 BRGCLK1/TOUT1/CLK2/PA9 TIN2/L1TCLKA/BRGO2/CLK3/PA10 TOUT2/CLK4/PA11 TIN3/BRGO3/CLK5/PA12 BRGCLK2/L1RCLKB/TOUT3/CLK6/PA13 TIN4/BRGO4/CLK7/PA14 L1TCLKB/TOUT4/CLK8/PA15 PORT B (PIP) RRJCT1/SPISEL/PB0 RSTRT2/SPICLK/PB1 RRJCT2/SPIMOSI(SPITXD)/PB2 BRGO4/SPIMISO(SPIRXD)/PB3 DREQ1/BRGO1/PB4 DACK1/BRGO2/PB5 DONE1/SMTXD1/PB6 DONE2/SMRXD1/PB7 DREQ2/SMSYN1/PB8 DACK2/SMSYN2/PB9 L1CLKOB/SMTXD2/PB10 L1CLKOA/SMRXD2/PB11 L1ST1/RTS1/PB12 L1ST2/RTS2/PB13 L1ST3/L1RQB/RTS3/PB14 L1ST4/L1RQA/RTS4/PB15 STRBO/BRGO3/PB16 STRBI/RSTRT1/PB17 PORT C (INTERRUPT PARALLEL I/O) L1ST1/RTS1/PC0 L1ST2/RTS2/PC1 L1ST3/L1RQB/RTS3/PC2 L1ST4/L1RQA/RTS4/PC3 CTS1/PC4 TGATE1/CD1/PC5 CTS2/PC6 TGATE2/CD2/PC7 SDACK2/L1TSYNCB/CTS3/PC8 L1RSYNCB/CD3/PC9 SDACK1/L1TSYNCA/CTS4/PC10 L1RSYNCA/CD4/PC11 DATA BUS D31D16 D15D0 PRTY1PRTY2/IOUT1IOUT2 PRTY2/IOUT0/RQOUT PRTY3/16BM BUS CONTROL SIZ0 SIZ1 DSACK0/TBI DSACK1/TA R/W AS DS/TT1 OE/AMUX BUS ARBITRATION RMC/CONFIG0/LOCK BR BG BGACK/BB BCLRO/CONFIG1/RAS2DD SYSTEM CONTROL QUICC TS68360 240 PINS RESETH RESETS HALT BERR/TEA PERR INTERRUPT CONTROL IRQ1/OUT0/RQOUT IRQ4/OUT1 IRQ6/OUT2 IRQ2,3,5,7 AVEC/IACK5/AVECO MEMORY CONTROLLER CS6CS0/RAS6RAS0 CS/RAS7/IACK7 CAS3CAS0/IACK6,3,2,1 TEST TRIS/TS BKPT/BKPT0/DSCLK FREEZE/CONFIG2/MBARE IPIPE1/RAS1DD/BCLRI IPIPE0/BADD2/DSO IFETCH/BADD3/DSI TCK TMS TDI TDO TRST CLOCK XTAL EXTAL XFC MODCK1MODCK0 CLKO2CLKO1
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Signal Index
Table 1. System Bus Signal Index (Normal Operation)
Group Address Signal Name Address Bus Address Bus/Byte Write Enables Function Codes Data Data Bus 31 - 16 Data Bus 15 - 0 Mnemonic A27-A0 A31-A28 WE3-WE0 FC3-FC0 D31-D16 D15-D0 Function Lower 27 bits of address bus. (I/O) Upper four bits of address bus (I/O), or byte write enable signals (O) for accesses to external memory or peripherals. Identifies the processor state and the address space of the current bus cycle. (I/O) Upper 16-bit data bus used to transfer byte or word data. Used in 16-bit bus mode. (I/O) Lower 16-bit data bus used to transfer 3-byte or long-word data. (I/O) Not used in 16-bit bus mode. Parity signals for byte writes/reads from/to external memory module. (I/O) Parity signals for byte writes/reads from/to external memory module or defines 16-bit bus mode. (I/O) Indicates a parity error during a read cycle. (O) Enables peripherals or DRAMs at programmed addresses (O) or interrupt level 7 acknowledge line. (O) Enables peripherals or DRAMs at programmed addresses. (O) DRAM column address select or interrupt level acknowledge lines. (O) Indicates that an external device requires bus mastership. (I) Indicates that the current bus cycle is complete and the QUICC has relinquished the bus. (O) Indicates that an external device has assumed bus mastership. (I) Identifies the bus cycle as part of an indivisible read-modify-write operation (I/O) or initial QUICC configuration select. (I) Indicates that an internal device requires the external bus (Open-Drain O) or initial QUICC configuration select (I) or row address select 2 double-drive output. (O)
Parity
Parity 2 - 0 Parity 3/16BM Parity Error
PRTY2-PRTY0 PRTY3/16BM PERR CS RAS7 IACK7 CS6-CS0 RAS6-RAS0 CAS3-CAS0/ IACK6,3,2,1 BR BG BGACK RMC CONFIG0 BCLRO/CONFIG1/ RAS2DD
Memory Controller
Chip Select Row Address Select 7 Interrupt Acknowledge 7 Chip Select 6-0 Row Address Select 6-0 Column Address Select 3 - 0/Interrupt Acknowledge 1, 2, 3, 6
Bus Arbitration
Bus Request Bus Grant Bus Grand Acknowledge Read-Modify-Write Cycle Initial Configuration 0 Bus Clear Out/Initial Configuration 1/Row Address Select 2 Double-Drive
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Table 1. System Bus Signal Index (Normal Operation) (Continued)
Group Bus Control Signal Name Data and Size Acknowledge Address Strobe Data Strobe Mnemonic DSACK1 - DSACK0 Function Provides asynchronous data transfer acknowledgement and dynamic bus sizing (open-drain I/O but driven high before three-stated). Indicates that a valid address is on the address bus. (I/O) During a read cycle, DS indicates that an external device should place valid data on the data bus. During a write cycle, DS indicates that valid data is on the data bus. (I/O) Indicates the number of bytes remaining to be transferred for this cycle. (I/O) Indicates the direction of data transfer on the bus. (I/O) Active during a read cycle indicates that an external device should place valid data on the data bus (O) or provides a strobe for external address multiplexing in DRAM accesses if internal multiplexing is not used. (O) Provides external interrupt requests to the CPU32+ at priority levels 7-1. (I) Autovector request during an interrupt acknowledge cycle (open-drain I/O) or interrupt level 5 acknowledge line. (O) Soft system reset. (open-drain I/O) Hard system reset. (open-drain I/O) Suspends external bus activity. (open-drain I/O) Indicates an erroneous bus operation is being attempted. (open-drain I/O) Internal system clock output 1. (O) Internal system clock output 2 - normally 2x CLKO1. (O) Connections for an external crystal to the internal oscillator circuit. EXTAL (I), XTAL (O). Connection pin for an external capacitor to filter the circuit of the PLL. (I) Selects the source of the internal system clock. (I) THESE PINS SHOULD NOT BE SET TO 00 Indicates when the CPU32+ is performing an instruction word prefetch (O) or input to the CPU32+ background debug mode. (I) Used to track movement of words through the instruction pipeline (O) or output from the CPU32+ background debug mode. (O) Used to track movement of words through the instruction pipeline (O), or a row address select 1 "double-drive" output (O). Signals a hardware breakpoint to the QUICC (open-drain I/O), or clock signal for CPU32+ background debug mode (I). Indicates that the CPU32+ has acknowledged a breakpoint (O), or initial QUICC configuration select (I).
AS DS
Size Read/Write Output Enable Address Multiplex
SIZ1-SIZ0 R/W OE/AMUX
Interrupt Control
Interrupt Request Level 7-1 Autovector/Interrupt Acknowledge 5
IRQ7-IRQ1 AVEC/IACK5 RESETS RESETH HALT BERR CLKO1 CLKO2 EXTAL, XTAL XFC MODCK1-MODCK0 IFETCH/DSI
System Control
Soft Reset Hard Reset Halt Bus Error
Clock and Test
System Clock Out 1 System Clock Out 2 Crystal Oscillator External Filter Capacitor Clock Mode Select 1-0 Instruction Fetch/ Development Serial Input Instruction Pipe 0/ Development Serial Output Instruction Pipe 1/Row Address Select 1 Double-Drive Breakpoint/Development Serial Clock Freeze/Initial Configuration 2
IPIPE0/DSO
IPIPE1/RAS1DD
BKPT/DSCLK FREEZE/CONFIG2
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Table 1. System Bus Signal Index (Normal Operation) (Continued)
Group Clock and Test (Cont'd) Signal Name Three-State Test Clock Test Mode Select Test Data In Test Data Out Test Reset Power Clock Synthesizer Power Clock Synthesizer Ground Clock Out Power Clock Out Ground Special Ground 1 Special Ground 2 System Power Supply and Return -Note: No Connect Mnemonic TRIS TCK TMS TDI TDO TRST VCCSYN GNDSYN VCCCLK GNDCLK GNDS1 GNDS2 VCC, GND NC4-NC1 Function Used to three-state all pins if QUICC is configured as a master. Always Sampled except during system reset. (I) Provides a clock for Scan test logic. (I) Controls test mode operations. (I) Serial test instructions and test data signal. (I) Serial test instructions and test data signal. (O) Provides an asynchronous reset to the test controller. (I) Power supply to the PLL of the clock synthesizer. Ground supply to the PLL of the clock synthesizer. Power supply to clock out pins. Ground supply to clock out pins. Special ground for fast AC timing on certain system bus signals. Special ground for fast AC timing on certain system bus signals. Power supply and return to the QUICC. Four no-connect pins.
1. I denotes input, O denotes output and I/O is input/output.
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Table 2. Peripherals Signal Index
Group SCC Signal Name Receive Data Transmit Data Request to Send Clear to Send Carrier Detect Receive Start Mnemonic RXD4-RXD1 TXD4-TXD1 RTS4-RTS1 CTS4-CTS1 CD4-CD1 RSTRT1 Function Serial receive data input to the SCCs. (I) Serial transmit data output from the SCCs. (O) Request to send outputs indicate that the SCC is ready to transmit data. (O) Clear to send inputs indicate to the SCC that data transmission may begin. (I) Carrier detect inputs indicate that the SCC should begin reception of data. (I) This output from SCC1 identifies the start of a receive frame. Can be used by an Ethernet CAM to perform address matching. (O) This input to SCC1 allows a CAM to reject the current Ethernet frame after it determines the frame address did not match. (I) Input clocks to the SCCs, SCMs, SI, and the baud rate generators. (I) A request (input) to an IDMA channel to start an IDMA transfer. (I) An acknowledgement (output) by the IDMA that an IDMA transfer is in progress. (O) A bidirectional signal that indicates the last IDMA transfer in a block of data. (I/O) An input to a timer that enables/disables the counting function. (I) Time reference input to the timer that allows it to function as a counter. (I) Output waveform (pulse or toggle) from the timer as a result of a reference value being reached. (O) Serial data input to the SPI master (I); serial data output from an SPI slave. (O) Serial data output from the SPI master (O); serial data input to an SPI slave. (I) Output clock from the SPI master (O); input clock to the SPI slave. (I) SPI slave select input. (I) Serial data input to the SMCs. (I) Serial data output from the SMCs. (O) SMC synchronization signal. (I)
Receive Reject
RRJCT1
Clocks IDMA DMA Request DMA Acknowledge
CLK8-CLK1 DREQ2-DREQ1 DACK2-DACK1
DMA Done TIMER Timer Gate Timer Input Timer Output SPI SPI Master In Slave Out SPI Master Out Slave In SPI Clock SPI Select SMC SMC Receive Data SMC Transmit Data SMC Sync
DONE2-DONE1 TGATE2-TGATE1 TIN4-TIN1 TOUT4-TOUT1 SPIMISO SPIMOSI SPICLK SPISEL SMRXD2-SMRXD1 SMTXD2-SMTXD1 SMSYN2-SMSYN1
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Table 2. Peripherals Signal Index (Continued)
Group SI Signal Name SI Receive Data SI Transmit Data SI Receive Clock SI Transmit Clock SI Transmit Sync Signals SI Receive Sync Signals IDL Interface Request SI Output Clock SI Data Strobes Mnemonic L1RXDA, L1RXDB L1TXDA, L1TXDB L1RCLKA, L1RCLKB L1TCLKA, L1TCLKB L1TSYNCA, L1TSYNCB L1RSYNCA, L1RSYNCB L1RQA, L1RQB L1CLKOA, L1CLKOB L1ST4-L1ST1 Function Serial input to the time division multiplexed (TDM) channel A or channel B. Serial output from the TDM channel A or channel B. Input receive clock to TDM channel A or channel B. Input transmit clock to TDM channel A or channel B. Input transmit data sync signal to TDM channel A or channel B. Input receive data sync signal to TDM channel A or channel B. IDL interface request to transmit on the D channel. Output from the SI. Output serial data rate clock. Can output a data rate clock when the input clock is 2x the data rate. Serial data strobe outputs can be used to gate clocks to external devices that do not have a built-in time slot assigner (TSA). Baud rate generator output clock allows baud rate generator to be used externally. Baud rate generator input clock from which BRG will derive the baud rates. PIP Data I/O Pins. This input causes the PIP output data to be placed on the PIP data pins. This input causes data on the PIP data pins to be latched by the PIP as input data. SDMA output signals used in RISC receiver to mark fields in the Ethernet receive frame.
BRG
Baud Rate Generator Out 4-1 BRG Input Clock
BRGO4-BRGO1 CLK2, CLK6 PB15-BP0 STRBO STRBI SDACK2-SDACK1
PIP
Port B 15-0 Strobe Out Strobe In
SDMA
SDMA Acknowledge 2-1
Scope
This drawing describes the specific requirements for the microcontroller TS68EN360 25 MHz and 33 MHz in compliance with MIL-STD-883 class B or Atmel standard screening.
Applicable Documents
MIL-STD-883
1. MIL-STD-883: test methods and procedures for electronics. 2. MIL-PRF-38535: general specifications for microcircuits. 3. DESC 5962-SMD-97607
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Requirements
General Design and Construction
Terminal Connections Depending on the package, the terminal connections shall be as shown in Figure 2 and Figure 3. Lead material and finish shall be as specified in MIL-STD-883 (see enclosed "Ordering Information" on page 79). The macrocircuits are packaged in hermetically sealed ceramic packages which are conform to case outlines of MIL-STD-1835 or as follow: * * PGA but see "241-pin - PGA" on page 77 CERQUAD This microcircuits are in accordance with the applicable document and as specified herein.
Lead Material and Finish
Package
The precise case outlines are described at the end of the specification ("Package Mechanical Data" on page 77) and into MIL-STD-1835.
Electrical Characteristics
Table 3. Absolute Maximum Ratings
Rating Supply Voltage Input Voltage
(1)(2)
Symbol VCC VIN TSTG
Value -0.3 to +6.5 -0.3 to +6.5 -55 to +150
Unit V V C
(1)(2)
Storage Temperature Range Note:
This device contains protective circuitry against damage due to high static voltages or electrical fields; however, it is advised that normal precautions be taken to avoid application of any voltages higher than maximum-rated voltages to this high-impedance circuit. Reliability of operation is enhanced if unused inputs are tied to an appropriate logic voltage level (e.g., either GND or VDD). 1. Permanent damage can occur if maximum ratings are exceeded. Exposure to voltages or currents in excess of recommended values affects device reliability. Device modules may not operate normally while being exposed to electrical extremes. 2. Although sections of the device contain circuitry to protect against damage from high static voltages or electrical fields, take normal precautions to avoid exposure to voltages higher than maximum-rated voltages. 3. The supply voltage VCC must start and restart from 0.0V; otherwise, the 360 will not come out of reset properly.Unless otherwise stated, all voltages are referenced to the reference terminal.
Notes:
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Table 4. Recommended Conditions Of Use Unless otherwise stated, all voltages are referenced to the reference terminal.
Symbol VCC VIL VIH Tcase VOH fsys Parameter Supply Voltage Range Logic Low Level Input Voltage Range Logic High Level Input Voltage Range Operating Temperature High Level Output Voltage System Frequency (For 25 MHz version) (For 33 MHz version) Min. +4.75 GND +2.0 -55 +2.4 25 33 Typ. Max. +5.25 +0.8 VCC +125 Unit V V V C V MHz MHz
Table 5. Thermal Characteristics
Symbol JC JA Parameter Thermal Resistance - Junction to Case 240-pin Cerquad 241-pin PGA Thermal Resistance - Junction to Ambient 240-pin Cerquad 241-pin PGA Value 2 7 27.4 22.8 Unit C/W C/W
TJ = TA + (PD * JA) PD = (VDD * IDD) + PI/O Where PI/O is the power dissipation on pins.
Power Considerations
The average chip-junction temperature, TJ, in C can be obtained from: TJ = TA / (PD * JA) (1) where: TA = Ambient Temperature, C JA = Package Thermal Resistance, Junction-to-Ambient, C/W PD = PINT + P I/O PINT = ICC * VCC, Watts-chip Internal Power PI/O = Power Dissipation on Input and Output Pins-User Determined For most applications, PI/O < 0.3 * PINT and can be neglected. An approximate relationship between PD and TJ (if PI/O is neglected) is: PD = K / (TJ + 273C) (2) Solving Equations (1) and (2) for K gives: K = PD * (TA + 273C) + JA * PD2 (3)
where K is a constant pertaining to the particular part. K can be determined from Equation (3) by measuring PD (at thermal equilibrium) for a know TA. Using this value of K, the values of PD and TJ can be obtained by solving Equations (1) and (2) iteratively for any value of TA.
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Mechanical and Environment Marking
The microcircuits shall meet all mechanical environmental requirements of either MIL-STD-883 for class B devices or for Atmel standard screening. The document where are defined the marking are identified in the related reference documents. Each microcircuit are legible and permanently marked with the following information as minimum: * * * * * * Atmel logo Manufacturer's part number Class B identification Date-code of inspection lot ESD identifier if available Country of manufacturing
Quality Conformance Inspection
DESC/MIL-STD-883
Is in accordance with MIL-M-38535 and method 5005 of MIL-STD-883. Group A and B inspections are performed on each production lot. Group C and D inspections are performed on a periodical basis.
Electrical Characteristics
General Requirements
All static and dynamic electrical characteristics specified for inspection purposes and the relevant measurement conditions are given below: * * Static electrical characteristics for the electrical variants Dynamic electrical characteristics for TS68EN360 (25 MHz, 33 MHz)
For static characteristics, test methods refer to IEC 748-2 method number, where existing. For dynamic characteristics, test methods refer to clause "Static Characteristics" on page 14 of this specification.
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Static Characteristics
GND = 0 Vdc, TC = -55 to +125C. The electrical specifications in this document are preliminary. (See numbered notes).
Characteristic Input High Voltage (except EXTAL) Input Low Voltage (5V Part) Input Low Voltage (Part Only; PA8-15, PB1, PC5, PC7, TCK) Input Low Voltage (Part Only; All Other Pins) EXTAL Input High Voltage Undershoot Input Leakage Current (All Input Only Pins except for TMS, TDI and TRST) Vin = 0/5V Hi-Z (Off-State) Leakage Current (All Noncrystal Outputs and I/O Pins except TMS,TDI and TRST) Vin = 0/5V Signal Low Input Current VIL = 0.8V (TMS, TDI and TRST Pins Only) Signal High Input Current VIH = 2.0V (TMS, TDI and TRST Pins Only) Output High Voltage IOH = -0.8 mA, VCC = 4.75V AII Noncrystal Outputs Except Open Drain Pins Output Low Voltage IOL = 2.0 mA, CLKO1-2, FREEZE, IPIPE0-1, IFETCH, BKPTO IOL = 3.2 mA, A31-A0, D31-D0, FC3-0, SIZ0-1, PA0, 2, 4, 6, 8-15, PB0-5, PB8-17, PC0-11, TDO, PERR, PRTY0-3, IOUT0-2, AVECO, AS, CAS3-0, BLCRO, RAS0-7 IOL = 5.3 mA, DSACK0-1, R/W, DS, OE, RMC, BG, BGACK, BERR IOL = 7 mA, TXD1-4 IOL = 8.9 mA, PB6, PB7, HALT, RESET, BR (Output) Input Capacitance AII I/O Pins Load Capacitance (except CLKO1-2) Load Capacitance (CLKO1-2) Power Symbol VIH VIL VIL VIL VIHC Iin IOZ IL IH VOH Min. 2.0 GND GND GND 0.8*(VCC) -2.5 -2.5 -0.5 -0.5 2.4 Max. VCC 0.8 0.5 0.8 VCC + 0.3 -0.8 2.5 -2.5 0.5 0.5 Unit V V V V V V A A mA mA V
0.5 0.5 VOL 0.5 0.5 0.5 Cin CL CLc VCC 4.75 20 100 50 5.25 pF pF pF V V
Dynamic Characteristics
The AC specifications presented consist of output delays, input setup and hold times, and signal skew times. All signals are specified relative to an appropriate edge of the clock and possibly to one or more other signals. The measurement of the AC specifications is defined by the waveforms shown in Figure 5. To test the parameters guaranteed by Atmel inputs must be driven to the voltage levels specified in the figure. Outputs are specified with minimum and/or maximum limits, as appropriate, and are measured as shown. Inputs are specified with minimum setup and hold times and are measured as shown. Finally, the measurement for signal-to-signal specifications are shown. Note that the testing levels used to verify conformance to the AC specifications do not affect the guaranteed DC operation of the device as specified in the DC electrical characteristics.
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Figure 5. Drive Levels and Test Points For AC Specifications
2.0V CLKOUT 0.8V A B OUTPUTS(1) VALID OUTPUT n 2.0V 0.8V 2.0V 0.8V VALID OUTPUT 0.8V 2.0V
n+1 B
A
OUTPUTS(2)
VALID OUTPUT n
2.0V 0.8V
2.0V 0.8V
VALID OUTPUT n+1
C 2.0V 0.8V
D 2.0V 0.8V
INPUTS(3)
VALID INPUT
C 2.0V 0.8V
D 2.0V 0.8V DRIVE TO 2.4V DRIVE TO 0.5V
INPUTS(4)
VALID INPUT
ALL SIGNALS(5)
2.0V 0.8V E F 2.0V 0.8V
Notes:
1. 2. 3. 4. 5.
This output timing is applicable to all parameters specified relative to the rising edge of the clock. This output timing is applicable to all parameters specified relative to the falling edge of the clock. This input timing is applicable to all parameters specified relative to the rising edge of the clock. This input timing is applicable to all parameters specified relative to the falling edge of the clock. This timing is applicable to all parameters specified relative to the assertion/negation of another signal.
Legend: a) Maximum output delay specification. b) Minimum output hold time. c) Minimum input setup time specification. d) Minimum input hold time specification. e) Signal valid to signal valid specification (maximum or minimum). f) Signal valid to signal invalid specification (maximum or minimum).
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AC Power Dissipation
Table 6. Typical Current Drain
Mode of Operation Normal mode (Rev A(1) and Rev B(2)) Normal Mode (Rev C Normal Mode Low Power Mode Low Power Mode Low Power Mode Low Power Mode Low Power Mode Low Power Stop VCO Off(4) PLL Supply Current PLL Disabled PLL Enabled Notes: 1. 2. 3. 4.
(3)
Symbol IDD IDD IDD IDDSB IDDSB IDDSB IDDSB IDDSB IDDSP IDDPD IDDPE
System Clock Frequency 25 MHz 25 MHz 33 MHz Divide by 2 12.5 MHz Divide by 4 6.25 MHz Divide by 16 1.56 MHz Divide by 256 97.6 kHz Divide by 256 97.6 kHz
BRGCLK Clock Frequency 25 MHz 25 MHz 33 MHz Divide by 16 1.56 MHz Divide by 16 1.56 MHz Divide by 16 1.56 MHz Divide by 16 1.56 MHz Divide by 64 390 kHz
SyncCLK Clock Frequency 25 MHz 25 MHz 33 MHz Divide by 2 12.5 MHz Divide by 4 6.25 MHz Divide by 4 6.25 MHz Divide by 4 6.25 MHz Divide by 64 390 kHz
Typ 250 237 327 150 85 35 20 13 0.5 TBD TBD
Unit mA mA mA mA mA mA mA mA mA
and Newer)
Rev A mask is C63T Rev B masks are C69T and F35G Current Rev C masks are E63C, E68C and F15W EXTAL frequency is 32 kHz
All measurements were taken with only CLKO1 enabled, VCC = 5.0V, VIL = 0V and VIH = VCC Table 7. Maximum Power Dissipation
System Frequency 25 MHz 25 MHz 25 MHz 33 MHz Notes: VCC 5.25V 5.25V 3.6V 5.25V Max PD 1.80 1.45 0.65 2.00 Unit W W W W REV A Mask
(1)
and REV B(2)
REV C(3) and Newer REV C(3) and Newer REV C(3) and Newer
1. Rev A mask is C63T 2. Rev B masks are C69T and F35G 3. Current Rev C masks are E63C, E68C and F15W
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AC Electrical Specifications Control Timing
GND = 0 Vdc, TC = -55 to +125C. The electrical specifications in this document are preliminary (See Figure 6).
25 MHz Number Characteristic System Frequency Crystal Frequency On-Chip VCO System Frequency Start-up Time With external clock (oscillator disabled) or after changing the multiplication factor MF CLKO1-2 stability 1 1A 1C 2, 3 2A, 3A 4, 5 4A, 5A 5B 5C 5D Note: CLKO1 Period EXTAL Duty Cycle, MF External Clock Input Period CLKO1 Pulse Width (Measured at 1.5V) CLKO2 Pulse Width (Measured at 1.5V) CLKO1 Rise and Fall Times (Full drive) CLKO2 Rise and Fall Times (Full drive) EXTAL to CLKO1 Skew-PLL enabled (MF< 5) EXTAL to CLKO2 Skew-PLL enabled (MF< 5) CLKO1 to CLKO2 Skew Symbol fsys fXTAL fsys tpll CLK tcyc tdcyc tEXTcyc tCW1 tCW2 tCrf1 tCrf2 tEXTP1 tEXTP2 AtmelKW TBD 40 40 40 19 9.5 Min dc
(1)
33.34 MHz Min Max 33.34 25 20 6000 67 Unit MHz kHz MHz clks % 30 40 30 14 7 60 2 1.6 a a a ns % ns ns ns ns ns ns ns ns
Max 25.00 6000 50 2500 TBD 60 2 2 a a a
25 20
1. Note that the minimum VCO frequency and the PLL default values put some restrictions on the minimum system frequency.
The following calculation should be used to determine the actual value for specifications 5B, 5C and 5D. 5B: 5C: 5D: 25 MHz 33 MHz 25 MHz 33 MHz (0.9 ns + 0.25 x (rise time)) (1.4 ns @ rise = 2 ns; 1.9 ns @ rise = 4 ns) (0.5 ns + 0.25 x (rise time)) (1 ns @ rise = 2 ns; 1.5 ns @ rise = 4 ns) (3 ns + 0.5 x (rise time)) (4 ns @ rise = 2 ns; 5 ns @ rise = 4 ns) (2.5 ns + 0.5 x (rise time)) (3.5 ns @ rise = 2 ns; 4.5 ns @ rise = 4 ns)
25/33 MHz (2 ns + 0.25 x (rise time)) (2.5 ns @ rise = 2 ns; 3 ns @ rise = 4 ns)
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Figure 6. Clock Timing
1A 1C EXTAL (INPUT) 5C CLKO1 (OUTPUT) 4 CLKO2 (OUTPUT) 4A 5A 2A 3A 2 5 5D 3 1 5B VOLTAGE MIDPOINT
External Capacitor For PLL
GND = 0 Vdc, TC = -55 to +125C. The electrical specifications in this document are preliminary.
Characteristic PLL External Capacitor (XFC to VCCSYN) MF< 5 (Recommended value MF x 400 pF)(1) MF> 4 (Recommended value MF x 540 pF) Note: 1. MF - multiplication factor.
(1)
Symbol cXFC
Min
Max
Unit
MF x 340 MF x 380
MF x 480 MF x 970
pF pF
Examples:
Notes: 1. MODCK1 pin = 0, MF = 1 CXFC = 400 pF 2. MODCK1 pin = 1, crystal is 32.768 kHz (or 4.192 MHz), initial MF = 401, initial frequency = 13.14 MHz, later on MF is changed to 762 to support a frequency of 25 MHz. Minimum CXFC is: 762 x 380 = 289 nF, Maximum CXFC is: 401 x 970 = 390 nF. The recommended CXFC for 25 MHz is: 762 x 540 = 414 nF. 289 nF < CXFC < 390 nF and closer to 414 nF. The proper available value for CXFC is 390 nF. 3. MODCK1 pin = 1, crystal is 32.768 kHz (or 4.192 MHz), initial MF = 401, initial frequency = 13.14 MHz, later on MF is changed to 1017 to support a frequency of 33.34 MHz. Minimum CXFC is: 1017 x 380 = 386 nF, Maximum CXFC is: 401 x 970 = 390 nF 386 nF < CXFC < 390 nF. The proper available value for CXFC is 390 nF. 4. In order to get higher range, higher crystal frequency can be used (i.e. 50 kHz), in this case: Minimum CXFC is: 667 x 380 = 253 nF, Maximum CXFC is: 401 x 970 = 390 nF 386 nF < CXFC < 390 nF.
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Bus Operation AC Timing Specifications
GND = 0 Vdc, TC = -55 to +125C. The electrical specifications in this document are preliminary (See Figure 7 to Figure 23).
25 MHz Number 6 6A 7 8 9 9(10) 9B 9A
(11)
33.34 MHz Min 0 0 0 -2 3 4 4 -5.625 9 8 22.5 3 4 4 12 7.5 22.5 56.25 26.25 26.25 26.25 10 26.25 7.5 22.5 0 Max 12 15 30 15 12 12 5.625 21 15 12 12 30 15 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Characteristic CLKO1 High to Address, FC, SIZ, RMC Valid CLKO1 High to Address Valid (GAMX = 1) CLKO1 High to Address, Data, FC, SIZ, RMC High Impedance CLKO1 High to Address, Data, FC, SIZ, RMC Invalid CLKO1 Low to AS, DS, OE, WE, IFETCH, IPIPE, IACKx Asserted CLKO1 Low to CSx/RASx Asserted CLKO1 High to CSx/RASx Asserted AS to DS or CSx/RASx or OE Asserted (Read) AS to CSx/RASx Asserted Address, FC, SIZ, RMC, valid to AS, CSx/RASx, OE, WE, (and DS Read) Asserted Address, FC, SIZ, RMC, Valid to CSx/RASx Asserted CLKO1 Low to AS, DS, OE, WE, IFETCH, IPIPE, IACKx Negated CLKO1 Low to CSx/RASx Negated CLKO1 High to CSx/RASx Negated CS negate to WE negate (CSNTQ = 1) AS, DS, CSx, OE, WE, IACKx Negated to Address, FC, SIZ Invalid (Address Hold) CSx Negated to Address, FC, SIZ, Invalid (Address Hold) AS, CSx, OE, WE (and DS Read) Width Asserted CSx Width Asserted DS Width Asserted (Write) AS, CSx, OE, WE, IACKx, (and DS Read) Width Asserted (Fast Termination Cycle) CSx Width Asserted (Fast Termination Cycle) AS, DS, CSx, OE, WE Width Negated CLKO1 High to AS, DS, R/W High Impedance AS, DS, CSx, WE Negated to R/W High CSx Negated to R/W High CLKO1 High to R/W High
Symbol tCHAV tCHAV tCHAZx tCHAZn tCLSA tCLSA tCHCA tSTSA tSTCA tAVSA tAVCA tCLSN tCLSN tCHCN AtmelTW tSNAI tCNAI tSWA tCWA tSWAW tSWDW tCWDW tSN tCHSZ tSNRN tCNRN tCHRH
Min 0 0 0 -2 3 4 4 -6 14 10 30 3 4 4 15 10 30 75 35 35 35 15 35 10 30 0
Max 15 20 40 20 16 16 6 26 20 16 16 40 20
(2)(10)
9C(2)(11) 11(10) 11A(11) 12 12(16) 12A
(13)(16)
12B 13(12) 13A(13) 14(10)(12) 14C
(11)(13)
14A 14B 14D(13) 15(3)(10)(12) 16 17
(12) (13)
17A
18
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Bus Operation AC Timing Specifications (Continued)
GND = 0 Vdc, TC = -55 to +125C. The electrical specifications in this document are preliminary (See Figure 7 to Figure 23).
25 MHz Number 20 21(10) 21A
(11)
33.34 MHz Min 3 7.5 Max 15 36 3 7.5 7.5 25 7.5 1 15 7.5 0 0 7.5 22.5 1 1 2 1 15 15 2.5 18 20 37.5 30 45 24 7.5 26 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns CLKO1 CLKO1 CLKO1 CLKO1
Characteristic CLKO1 High to R/W Low R/W High to AS, CSx, OE Asserted R/W High to CSx Asserted R/W Low to DS Asserted (Write) CLKO1 High to Data-Out CLKO1 High to Parity Valid Parity Valid to CAS Low Data-Out, Parity-Out Valid to Negating Edge of AS, CSx, WE, (Fast Termination Write) DS, CSX, WE Negated to Data-Out, Parity-Out Invalid (Data-Out, Parity-Out Hold) CSx Negated to Data-Out, Parity-Out Invalid (DataOut, Parity-Out Hold) Data-Out, Parity-Out Valid to DS Asserted (Write) Data-In, Parity-In to CLKO1 Low (Data-Setup) Data-In, Parity-In Valid to CLKO1 Low (Data-Setup) Late BERR, HALT, BKPT Asserted to CLKO1 Low (Setup Time) AS, DS Negated to DSACKx, BERR, HALT Negated DS, CSx, OE, Negated to Data-In Parity-In Invalid (Data-In, Parity-In Hold) DS, CSx, OE Negated to Data-In High Impedance CLKO1 Low to Data-In, Parity-In Invalid (Fast Termination Hold) CLKO1 Low to Data-In High Impedance DSACKx Asserted to Data-in, Parity-In Valid DSACKx Asserted to DSACKx Valid (Skew) DSACKx Asserted to Data-in, Parity-In Valid HALT an RESET Input Transition Time CLKO1 High to BG Asserted CLKO1 High to BG Negated BR Asserted to BG Asserted (RMC Not Asserted) BGACK Asserted to BG Negated BG Width Negated BG Width Asserted
Symbol tCHRL tRAAA tRACA tRASA tCHDO tCHPV tPVCL tDVASN tSNDOI tCNDOI tDVSA tDICL tDICL tBELCL tSNDN tSNDI tSHDI tCLDI tCLDH tDADI tDADV tDADI tHRrf tCLBA tCLBN tBRAGA tGAGN tGH tGA
Min 3 10 30 47 3 10 10 35 10 1 20 10 0 0 10 1 1 2 1
Max 20 23 25 50 40 60 32 10 35 140 20 20 2.5 -
22 23 23A 23B 24(12) 25(12) 25A(13) 26 27
(15)
27B(14) 27A 28(18) 29(4) 29A(4) 30(4) 30A(4) 31
(5)(15)
31A 31B
(5)(14)
32 33 34 35(6) 37 39 39A
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Bus Operation AC Timing Specifications (Continued)
GND = 0 Vdc, TC = -55 to +125C. The electrical specifications in this document are preliminary (See Figure 7 to Figure 23).
25 MHz Number 46 46A 47A 47B 48
(5)(7)
33.34 MHz Min 75 56 4 7.5 0 19 512 20 0 Max 22.5 15 26 26 3.75 7.5 3.75 7.5 5 0 7.5 3.75 7.5 3.75 0 10 7.5 15 15 15 22.5 500 Unit ns ns ns ns ns ns ns ns CLKO1 CLKO1 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns CLKO1 ns CLKO1 ns
Characteristic R/W Width Asserted (Write or Read) R/W Width Asserted (Fast Termination Write or Read) Asynchronous Input Setup Time Asynchronous Input Hold Time DSACKx Asserted to BERR, HALT Asserted Data-Out, Parity-Out Hold from CLKO1 High CLKO1 High to Dat-Out, Parity-Out High Impedance R/W Asserted to Data Bus Impedance Change RESET Pulse Width (Reset Instruction) RESET Pulse Width (Input from External Device) BERR Negated to HALT Negated (Return) CLKO1 High to BERR, RESETS, RESETH Driven Low CLKO1 Low RESETS Driven Low (upon Reset Instruction execution only) CLKO1 High to BERR, RESETS, RESETH tri-stated CLKO1 High to BCLRO Asserted CLKO1 High to BCLRO Negated BR Synchronous Setup Time BR Synchronous Hold Time BGACK Synchronous Setup Time BGACK Synchronous Hold Time BR Low to CLKO1 Rising Edge (040 comp. mode) CLKO1 Low to Data Bus Driven (Show Cycle) Data Setup Time to CLKO1 Low (Show Cycle) Data Hold from CLKO1 Low (Show Cycle) BKPT Input Setup Time BKPT Input Hold Time RESETH Low to Config2-0, MOD1-0, B16M Valid Config2-0 MOD1-0 Hold Time, B16M Hold Time DSI Input Setup Time
Symbol tRWA tRWAS tAIST tAIHT tDABA tDOCH tCHDH tRADC tHRPW tRPWI tBNHN tCHBRL tCLRL tCLRL tCHBCA tCHBCN tBRSU tBRH tBGSU tBGH tBRCH tSCLDD tSCLDS tSCLDH tBKST tBKHT tMST tMSH tMSH tDSISU
Min 100 75 5 10 0 25 512 20 0 5 10 5 10 5 0 10 6 10 6 0 10 10
Max 30 20 30 30 20 20 20 30 500 -
53 54 55 56 56A 57 58 58A 58B 60 61 62 63
(9) (9)
64(9) 65
(9)
66 70 71 72 73 74 75 76 77 80
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Bus Operation AC Timing Specifications (Continued)
GND = 0 Vdc, TC = -55 to +125C. The electrical specifications in this document are preliminary (See Figure 7 to Figure 23).
25 MHz Number 81 82 83 84 85 86 87 88 89 90 91 92 Notes: Characteristic DSI Input Hold Time DSCLC Setup Time DSCLC Hold Time DSO Delay Time DSCLK Cycle CLKO1 High to Freeze Asserted CLKO1 High to Freeze Negated CLKO1 High to IFETCH High Impedance CLKO1 High to IFETCH Valid CLKO1 High to PERR Asserted CLKO1 High to PERR Negated VCC Ramp-Up Time At Power-On Reset Symbol tDSIH tDSCSU tDSCH tDSOD tDSCCYC tFRZA tFRZN tIFZ tIF tCHPA tCHPN tRMIN Min 6 10 6 2 0 0 0 0 0 0 5 Max tcyc+2 0 35 35 35 35 20 20 33.34 MHz Min 3.75 7.5 3.75 2 0 0 0 0 0 0 5 Max tcyc+2 0 26.25 26.25 26.25 26.25 15 15 Unit ns ns ns ns CLKO1 ns ns ns ns ns ns ns
1. All AC timing is shown with respect to 0.8V and 2.0V levels unless otherwise noted. 2. This number can be reduced to 5 ns if strobes have equal loads. 3. If multiple chip selects are used, the CSx width negated (#15) applies to the time from the negation of a heavily loaded chip select to the assertion of a lightly loaded chip select. 4. Hold times are specified with respect to DS or CSx on asynchronous reads and with respect to CLKO1 on fast termination reads. The user is free to use either hold time for fast termination reads. 5. If the asynchronous setup (#17) requirements are satisfied, the DSACKx low to data setup time (#31) and DSACKx low to BERR low setup time (#48) can be ignored. The data must only satisfy the data-in to CLKO1 low setup time (#27) for the following clock cycle: BERR must only satisfy the late BERR low to CLKO1 low setup time (#27A) for the following clock cycle. 6. To ensure coherency during every operand transfer, BG will not be asserted in response to BR until after cycles of the current operand transfer are complete and RMC is negated. 7. In the absence of DSACKx, BERR is an asynchronous input using the asynchronous setup time (#47). 8. During interrupt acknowledge cycles, the processor may insert up to two wait states between states S0 and S1. 9. Specs are for Synchronous Arbitration only. ASTM = 1. 10. CSx specs are for TRLX = 0. 11. CSx specs are for TRLX = 1. 12. CSx specs are for CSNTQ = 0. 13. CSx specs are for CSNTQ = 1; or RASx specs for DRAM accesses. 14. Specs are read cycles with parity check and PBEE = 1. 15. Specs are read cycles with parity check and PBEE = 0, PAREN = 1. 16. RASx specs are for page miss case. 17. Specifications only apply to CSx/RASx pins. 18. Specification applies to non fast termination cycles. In fast termination cycles, the BERR signal must be negated by 20 ns after negation of AS, DS.
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Figure 7. Read Cycle
S0 CLKO1 (OUTPUT) 6 A31-A0 (OUTPUT) FC3-FC0 (OUTPUT) SIZ1-SIZ0 (OUTPUT) RMC (OUTPUT) 11 AS (OUTPUT) 9 DS (OUTPUT) 9A CSx (OUTPUT) OE (OUTPUT) 18 R/W (OUTPUT) DSACK0 (I/O) 47A DSACK1 (I/O) D31-D0 (INPUT) 28 14 12 16 8 S1 S2 S3 S4 S5
13 15
21
20
46
31A 31 27 48 27A
29
29A
BERR, HALT (INPUT) IFETCH IPIPE1,0 (OUTPUT) ASYNCHRONOUS INPUTS
9
12
12
47A
47B
73 BKPT (INPUT)
74
Note:
All timing is shown with respect to 0.8V and 2.0V levels.
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Figure 8. Fast Termination Read Cycle (Parity Check PAREN = 1, PBEE = 0)
CPU CLEARS PERn BIT S0 CLKO1 (OUTPUT) 6 A31-A0 (OUTPUT) FC3-FC0 (OUTPUT) SIZ1-SIZ0 (OUTPUT) 9 14B AS (OUTPUT) 12 DS (OUTPUT) CSx (OUTPUT) OE (OUTPUT) R/W (OUTPUT) D31-D0 (INPUT) 30A 73 BKPT (INPUT) 90 PERR (OUTPUT) 91 74 8 S1 S4 S5 S0 S0
18
46A 27 30
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Figure 9. Read Cycle (With Parity Check, PBEE = 1)
S0
CLKO1 (OUTPUT)
S1
S2
S3
S4
S5
6 A31-A0, FC3-FC0, SIZ1-SIZ0 (OUTPUT) RMC (OUTPUT) 11 14 AS (OUTPUT) 9 DS (OUTPUT) 9A CSx (OUTPUIT) OE (OUTPUT) 18 R/W (OUTPUT) 31A
DSACK0 (I/O)
8
16
12
13 15
21
20
46
47A
DSACK1 (I/O)
28
PRTY0-PRTY3 (INPUT) 31B D31-D0 (INPUT) 29A 27B BERR (INPUT) HALT (INPUT) 48 27A 29
9
12
12
IFETCH (OUTPUT) 47A IPIPE1,0 (OUTPUT) ASYNCHRONOUS INPUTS 73 BKPT (INPUT) 74 47B
Note:
All timing is shown with respect to 0.8V and 2.0V levels.
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Figure 10. SRAM: Read Cycle (TRLX = 1)
S0 CLKO1 (OUTPUT) 6 A31-A0 (OUTPUT) FC3-FC0 (OUTPUT) SIZ1-SIZ0 (OUTPUT) RMC (OUTPUT) 9C AS (OUTPUT) 11A DS (OUTPUT) 9B CSx (OUTPUT) 21A OE (OUTPUT) R/W (OUTPUT) 46 28 DSACK0 (I/O) 47A DSACK1 (I/O) D31-D0 (INPUT) 29A 27 20 15 12 13 16 8 S1 S2 S3 S4 S5
18
31A 31
29
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Figure 11. CPU32+ IACK Cycle
0-2 CLOCKS * S0 CLKO1 (OUTPUT) 6 A31-A0 (OUTPUT) FC3-FC0 (OUTPUT) SIZ1-SIZ0 (OUTPUT) 11 AS (OUTPUT) 9 DS (OUTPUT) 9A IACKx (OUTPUT) OE (OUTPUT) 18 R/W (OUTPUT) 31A DSACK0 (I/O) 47A DSACK1 (I/O) D31-D0 (INPUT) 29A 27 31 29 21 20 12 15 14 16 8 A1 A2 A3 A4 S1 S2 S3 S4 S5
13
46 28
Note:
Up to two wait states may be inserted by the processor between states S0 and S1.
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Figure 12. Write Cycle
S0 CLKO1 (OUTPUT) 6 A31-A0 (OUTPUT) FC3-FC0 (OUTPUT) SIZ1-SIZ0 (OUTPUT) 11 14 AS (OUTPUT) 9 DS (OUTPUT) 14A CSn (OUTPUT) 22 WEn (OUTPUT) R/W (OUTPUT) 46 DSACK0 (I/O) 31A 47A DSACK1 (I/O) 55 D31-D0 (OUTPUT) PRTY3-PRTY0 (OUTPUT) BERR (INPUT) 48 HALT (INPUT) BKPT (INPUT) 73 74 25 53 28 17 9 12 13 15 8 S1 S2 S3 S4 S5
20
18
23 26
54
Note:
All timing is shown with respect to 0.8V and 2.0V levels.
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Figure 13. Fast Termination Write Cycle
S0 CLKO1 (OUTPUT) A31-A0 (OUTPUT) FC3-FC0 (OUTPUT) SIZ1-SIZ0 (OUTPUT) 12 AS (OUTPUT) 9 CSx (OUTPUT) DS (OUTPUT) WEx (OUTPUT) R/W (OUTPUT) 23 D31-D0 (OUTPUT) 25 PRTY3-PRTY0 (OUTPUT) 73 BKPT (INPUT) 74 24 18 14B S1 S4 S5 S0
6
8
20 46A
Figure 14. SRAM: Fast Termination Write Cycle (CSNTQ = 1)
S0 CLKO1 (OUTPUT) 6 A31-A0 (OUTPUT) FC3-FC0 (OUTPUT) SIZ1-SIZ0 (OUTPUT) AS (OUTPUT) 9 14D CSx (OUTPUT) DS (OUTPUT) WEx (OUTPUT) R/W (OUTPUT) 23 D31-D0 (OUTPUT) 25A PRTY3-PRTY0 (OUTPUT) 18 12A 8 S1 S4 S5 S0
20 46A
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Figure 15. SRAM: Write Cycle (TRLX = 1, CSNTQ = 1, TCYC = 0)
S0 CLKO1 (OUTPUT) A31-A0 (OUTPUT) AS (OUTPUT) 9C DS (OUTPUT) 11A 9B CSx (OUTPUT) 14C WEx (OUTPUT) R/W (OUTPUT) 20 22 46 47A DSACK0 (I/O) 31A DSACK1 (I/O) D31-D0 (OUTPUT) 23 PRTY0-PRTY3 (OUTPUT) 55 26 25A 17A 13A 12A S1 S2 S3 S4 S5
Note:
All timing is shown with respect to 0.8V and 2.0V levels.
Figure 16. ASYNC Bus Arbitration - IDLE Bus Case
CLKO1 (OUTPUT) A31-A0 (OUTPUT) D31-D0 (OUTPUT) AS (OUTPUT) BR (INPUT) 35 BG (OUTPUT) 33 BGACK (INPUT) 47A BCLRO (OUTPUT) 60 61 34 47A 37
47A
47A
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Figure 17. ASYNC Bus Arbitration - Active Bus Case
S0 CLKO1 (OUTPUT) A31-A0 (OUTPUT) S1 S2 S3 S4 S5
7
D31-D0 (OUTPUT) AS (OUTPUT)
16
DS (OUTPUT) R/W (OUTPUT) DSACK0 (I/O) DSACK1 (I/O)
47A
BR (INPUT)
47A
35
BG (OUTPUT)
39A
33
BGACK (INPUT)
34
47A 37
BCLRO (OUTPUT) 60
Figure 18. SYNC Bus Arbitration - IDLE Bus Case
CLKO1 (OUTPUT) A31-A0 (OUTPUT) D31-D0 (OUTPUT) AS (OUTPUT) BR (INPUT) 35 BG (OUTPUT) 33 BGACK (INPUT) 64 BCLRO (OUTPUT) 60 61 34 65 37
62
63
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Figure 19. SYNC Bus Arbitration - Active Bus Case
S0 CLKO1 (OUTPUT) A31-A0 (OUTPUT) S1 S2 S3 S4 S5 S98
7
D31-D0 (OUTPUT) AS (OUTPUT)
16
DS (OUTPUT) R/W (OUTPUT) DSACK0 (I/O) DSACK1 (I/O)
62
BR (INPUT)
35
BG (OUTPUT)
39A
33
BGACK (INPUT) 64 BCLRO (OUTPUT)
34
37
60
Figure 20. Configuration and Clock Mode Select Timing
RESETH
CONFIG2-CONFIG0, 76 MODCK1-MODCK0, 16BM 75 77
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Figure 21. Show Cycle
S0 CLKO1 (OUTPUT) 6 A31-A0 (OUTPUT) 18 R/W (OUTPUT) 20 AS (OUTPUT) 9 DS (OUTPUT) 70 D31-D0 27A BKPT (INPUT) SHOW CYCLE START OF EXTERNAL CYCLE 71 72 12 15 8 S41 S42 S43 S0 S1 S2
Figure 22. Background Debug Mode FREEZE Timing
CLKO1
86 FREEZE 87
IFETCH/DSI 88 89
Figure 23. Background Debug Mode Serial Port Timing
CLKO1
FREEZE 82 83
BKPT/DSCLK 80 81 IFETCH 84 IPIPE0/DSO 85 DSI 80
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Bus Operation - DRAM Accesses AC Timing Specification
GND = 0 Vdc, TC = -55 to +125C. The electrical specifications in this document are preliminary (See Figure 24 to Figure 28).
25.0 MHz Number 100 101 102 103A 103B 103C 103D 104 105 105A 106 107 108 109 110 1111 111A 113 114 115 116 117 119 120 121 122 123 124 125 Characteristic RASx Asserted to Row Address Invalid RASx Asserted to column Address Valid RASx Width Asserted RASx width Negated (Back to back Cycle) Non page mode @ WBTQ = 0 RASx width Negated (Back to back Cycle) Page mode @ WBTQ = 0 RASx width Negated (Back to back Cycle) Non page mode @ WBTQ = 1 RASx width Negated (Back to back Cycle) Page mode @ WBTQ = 1 RASx Asserted to CASx Asserted CLKO1 Low to CASx Asserted CLKO1 High to CASx Asserted (Refresh Cycle) CLKO1 High to CASx Negated Column Address Valid to CASx Asserted CASx Asserted to Column Address Negated CASx Asserted to RASx Negated CASx Width Asserted CASx Width Negated (Back to Back Cycles) CASx Width Negated (Page Mode) WE Low to CASx Asserted CASx Asserted to WE Negated R/W Low to CASx Asserted (Write) CASx Asserted to R/W High (Write) Data-Out, Parity-Out Valid to CASx Asserted CLKO1 High to AMUX Negated CLKO1 High to AMUX Asserted AMUX High to RASx Asserted RASx Asserted to AMUX Low AMUX Low to CASx Asserted CASx Asserted to AMUX High RAS/CASx Negated to R/W change Min 15 20 75 75 55 115 95 35 3 3 3 15 40 35 50 95 20 35 35 52.5 55 10 3 3 15 15 15 55 0 16 16 13 13 13 Max 33.34 MHz Min 11.25 15 56.25 56.25 41.25 86.25 69.23 26.25 2 2 2 11.25 30 27 37.5 71.25 15 27 27 40 41.25 7.5 2 2 11.25 11.25 11.25 41.25 0 12 12 10 10 10 Max ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Unit
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Figure 24. DRAM: Normal Read Cycle (Internal Mux, TRLX = 0)
S0 CLKO1 (OUTPUT) 6 A31-A0 (OUTPUT) 11 AS (OUTPUT) 9 100 RASx (OUTPUT) 101 102 104 CAS3-CAS0 (OUTPUT) OE (OUTPUT) 21 18 R/W (OUTPUT) 105 109 110 111 106 103 107 108 6A 8 S1 S2 S3 S4 S5 S0 S1 S2 S3 SW SW
12
9
DSACK1,0 (I/O) 27 D31D0 (INPUT) PBEE = 0 PARITY3-PARITY0 (INPUT) PBEE = 1 D31-D0 (INPUT) 29 27B
Note:
All timing is shown with respect to 0.8V and 2.0V levels.
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Figure 25. DRAM: Normal Write Cycle
S0 CLKO1 (OUTPUT) 6 A31-A0 (OUTPUT) 11 AS (OUTPUT) 9 100 RASx (OUTPUT) 101 102 106 CAS3-CAS0 (OUTPUT) 105 113 WEx (OUTPUT) 20 115 R/W (OUTPUT) 17 DSACK1,0 (I/O) 117 D31-D0 (OUTPUT) 23 PARITY0-PARITY3 (OUTPUT) 53 116 114 110 107 108 6A 8 S1 S2 S3 S4 S5 S0
12
Note:
All timing is shown with respect to 0.8V and 2.0V levels.
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Figure 26. DRAM: Refresh Cycle
S4 CLKO1 (OUTPUT) A31-A0 (OUTPUT) 106 CAS3-CAS0 (OUTPUT) 105A 12 RASx (OUTPUT) 12A RASx (OUTPUT) NOT IN PAGE MODE PAGE MODE 9 12 S5 S0 S1
Note:
All timing is shown with respect to 0.8V and 2.0V levels.
Figure 27. DRAM: Page Mode - Page-Hit
S0 CLKO1 (OUTPUT) 6A A31-A0 (OUTPUT) INTERNAL MUX INTERNAL MUX AS (OUTPUT) 9 100 RASx (OUTPUT) 101 106 CAS3-CAS0 (OUTPUT) 121 122 AMUX (OUTPUT) 119 120 124 105 123 111A 105 11 107 108 107 6A 8 S1 S2 S3 S4 S5 S0 S1 S4 S5 S0 S1
EXTERNAL MUX
Note:
All timing is shown with respect to 0.8V and 2.0V levels.
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Figure 28. DRAM: Page Mode - Page-Miss
S0 CLKO1 (OUTPUT) 6A A31-A0 (OUTPUT) INTERNAL MUX AS (OUTPUT) 9 RASn (OUTPUT) 106 CAS3-CAS0 (OUTPUT) 105 122 AMUX (OUTPUT) 120 EXTERNAL MUX 119 120 123 12A 11 6A 8 S1 S2 S3 S4 S5 S0 S1 S2 S3 SW SW
Note:
All timing is shown with respect to 0.8V and 2.0V levels.
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040 Bus Type Slave Mode Bus Arbitration AC Electrical Specifications GND = 0 Vdc, TC = -55 to +125C. The electrical specifications in this document are preliminary (See Figure 29).
25.0 MHz Number 231 232
(1)
33.34 MHz Min 6 4 6 0 Max 15 15 15 15 15 Unit ns ns ns ns ns ns ns ns
Characteristic Address, Transfer Attributes High Impedance to Clock High Clock High to BG Low Clock High to BG High BB High to Clock High (040 output) BB High Impedance to Clock High (040 output) Clock High to BB Low (360 Output) Clock High to BB High (360 Output) Clock Low to BB High Impedance (360 output)
Min 7 4 7 0 -
Max 20 20 20 20 20
233 234 235 236 237 238 Note:
1. BG remains low until either the SDMA or the IDMA requests the external bus.
Figure 29. TS68040 Companion Mode Arbitration
040 BUS MASTER
C1 CLKO1 (OUTPUT) A31-A0 (I/O) 231 TRANSFER ATTRIBUTES (INPUT) 233 BG (OUTPUT) 234 BB (I/O) 237 232 C2 S0 S1
360 BUS MASTER
S2 S3 S4 S5
235 236 60 61
238
BCLRO (OUTPUT) 140 BCLRI (INPUT) 141
Notes:
1. TS68040 Transfer Attribute Signals = SIZx, TTx, TMx, R/W, LOCK. 2. BG always remains asserted until either the SDMA or the IDMA requests the external bus.
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040 Bus Type Slave Mode Internal Read/Write/Lack Cycles AC Electrical Specifications
GND = 0 Vdc, TC = -55 to +125C. The electrical specifications in this document are preliminary (See Figure 30 to Figure 33)
25.0 MHz Number 251
(1)
33.34 MHz Min 11.25 6 3 0 0 0 4 4 4 15 23 23 23 23 Max 15 18 15 11.25 15 15 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Characteristic Address, Transfer Attributes Valid to Clock Low TS Low to Clock High Clock High to TS High Clock high to Address, Transfer Attributes Invalid Data-In, MBARE Valid to Clock High (040 Write) Clock High to Data-In, MBARE Hold Time Clock High to TA, TBI Low (External to External) Clock High to TA, TBI Low (External to Internal) Clock High to TA, TBI High TA, TBI High to TA, TBI High Impedance Clock Low to Data-Out Valid (040 Read) Clock Low to Data-Out Invalid Clock Low to Data-Out High Impedance Clock High to AVECO Low Clock Low to AVECO High Impedance Clock Low to IACK Low Clock High to IACK High Clock Low to AVEC Low
Min 15 7 5 0 0 0 4 4 4 -
Max 20 23 20 15 20 20 15 20 30 30 30 30
252 253 254 255 256 257 257 258
(2)(3)
259 260 262 263 264 265 266 267 268 Notes:
1. Transfer attributes signals = SIZx, TTx, TMx, R/W and LOCK. 2. When TS68040 is accessing the internal registers, specification 258 is from clock low not clock high. 3. The clock reference is EXTAL, not CLK01.TS68040 Internal Registers Read Cycles
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Figure 30. TS68040 Internal Registers Read Cycles
C1 CLKO1 (OUTPUT) 251 A31-A0 (INPUT) 254 TRANSFER ATTRIBUTES (INPUT) TS (INPUT) D31-D0 (040 WRITE) (INPUT) TA (OUTPUT) 257 TBI (OUTPUT) 34 CLOCKS 258 259 252 C2 CW CW CW CW C1
253 260 263
Notes:
1. Three wait states are inserted when reading the SIM, dual-port RAM, and CPM. Four wait states are inserted when reading the SI RAM. Additional wait states may be inserted when the SHEN1-SHEN0 = 10 and one of the internal masters is accessing an internal peripheral. 2. TS68040 Transfer Attribute Signals = SIZx, TTx, TMx, R/W, LOCK.
Figure 31. TS68040 Internal Registers Write Cycles
C1 CLKO1 (OUTPUT) 251 A31-A0 (INPUT) 254 TRANSFER ATTRIBUTES (INPUT) 252 TS (INPUT) D31-D0 (040 WRITE) (INPUT) MBARE (INPUT) TA (OUTPUT) 257 TBI (OUTPUT) 258 259 253 255 256 C2 CW CW CW C1
255
256
2N4 CLOCKS
Notes:
1. Two wait states are inserted when writing. Three wait states are inserted when writing to the dual-port RAM and CPM. Four wait states are inserted when writing to the SI RAM. Additional wait states may be inserted when the SHEN1-SHEN0 = 10 and one of the internal masters is accessing an internal peripheral. 2. TS68040 Transfer Attribute Signals = SIZx, TTx, TMx, R/W, LOCK.
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Figure 32. TS68040 IACK Cycles (Vector Driven)
C1 CLKO1 (OUTPUT) 251 A31-A0 (INPUT) TRANSFER ATTRIBUTES (INPUT) 252 TS (INPUT) D31-D0 (OUTPUT) 260 TA (OUTPUT) 257 TBI (OUTPUT) IACK7-1 (OUTPUT) 266 02 CLOCKS 267 258 259 254 C2 CW CW CW CW CW
253 263 262
Notes:
1. TS68040 Transfer Attribute Signals = SIZx, TTx, TMx, R/W, LOCK. 2. Up to two wait states may be inserted for internal peripheral.
Figure 33. TS68040 IACK Cycles (No Vector Driven)
C1 CLKO1 (OUTPUT) 251 A31-A0 (INPUT) TRANSFER ATTRIBUTES (INPUT) 252 TS (INPUT) TA (INPUT) 289 TBI (OUTPUT) 257 AVECO (OUTPUT) 264 IACK7-1 (OUTPUT) 266 267 265 250 290 254 C2 CW CW
253
Note:
TS68040 Transfer Attribute Signals = SIZx, TTx, TMx, R/W, LOCK.
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040 Bus Type SRAM/DRAM Cycles AC Electrical Specifications
GND = 0 Vdc, TC = -55 to +125C. The electrical specifications in this document are preliminary (See Figure 34 to Figure 38).
25.0 MHz Number 280 280A 281 282 283 284 284A 285 286 287 288 289 290
(1) (2) (2)
33.34 MHz Min 10 0 4 4 4 4 10 9 4 4 4 3 3 4 Max 15 12 12 15 15 15 12 12 15 15 15 15 15 10 10 10 12 12 15 2 6 5 15 15 15 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Characteristic Address Valid to BADD2-3 Valid BADD2-3 Valid to CAS Assertion Address Invalid to BADD2-3 Invalid Clock High to CSx/RASx Low (TSS40 = 0) Clock High to CSx/RASx High (CSNT40 = 0) Clock High to BRK Low Clock Low to BRK Low Clock high to BRK High Clock Low to CSx/RASx Low (TSS40 = 1) Clock Low to CSx/RASx High (CSNT40 = 1) Address Transfer Attributes Valid to Clock High (TSS40 = 0) TA Low to Clock High (External Termination) Clock High to TA High (External Termination) Clock High to OE Low (Read Cycles) Clock High to OE High (Read Cycles) Clock High to WE Low (Write Cycles) Clock High to WE High (Write Cycles) Clock High to CASx Low Clock Low to CASx Low (040 Burst Read only) Clock High to CASx High Clock Low to AMUX Low Clock High to AMUX High Clock High to BADD2-3 Valid (040 Burst Cycles) TEA Low to Clock High Clock High to TEA High Data, Parity Valid to Clock High (Data, Parity Setup) Clock High to Data, Parity Invalid (Data, Parity Hold) CLKO1 High (After TS Low) to Parity Valid CLKO1 High (After TA Low) to Parity Hi-Z
Min 15 0 4 4 4 4 10 11 4 4 4 3 3 4 11 2 7 7 4
Max 20 16 16 20 20 20 16 16 20 20 20 20 20 13 13 13 16 16 20 20 20 20
291 292 293 294 295 295A 296
(3)
297 298 299 300 301
(2) (2)
302 303 305 306 Notes:
1. Transfer attributes signals = SIZx, TTx, TMx, R/W and LOCK. 2. TEA/TA should not be asserted on a DRAM burst access, or on the same clock or before RASx/CSx is asserted. 3. The clock reference is EXTAL, not CLK01.
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Figure 34. TS68040 SRAM Read/Write Cycles (TSS40 = 0, CSNT40 = 0)
C1 CLKO1 (OUTPUT) 288 TRANSFER ATTRIBUTES (INPUT) 254 A31-A0 (INPUT) 280 BADD3BADD2 (OUTPUT) TS (INPUT) 252 253 281 C2
282 CSx (OUTPUT) TA (OUTPUT) 257 TBI (OUTPUT) 284 BKPTO (OUTPUT) OE (OUTPUT) (READ CYCLES) WE (OUTPUT) (WRITE CYCLES) TEA (INPUT) 291
283
258 259
285
292
293
294
300
301
Note:
TS68040 Transfer Attribute Signals = SIZx, TTx, TMx, R/W, LOCK.
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Figure 35. TS68040 SRAM Read/Write Cycles (TSS40 = 1, CSNT40 = 1)
C1 CLKO1 (OUTPUT) 251 TRANSFER ATTRIBUTES (INPUT) A31-A0 (INPUT) 280 BADD3BADD2 (OUTPUT) 253 TS (INPUT) 252 281 C2 C3
254
287 CSn (OUTPUT) 286 258 TA (OUTPUT) 257 TBI (OUTPUT) 284A BKPTO (OUTPUT) 300 TEA (INPUT) TA (INPUT) 289 290 301 259
285
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Figure 36. External TS68040 DRAM Cycles Timing Diagram
C1 CLKO1 (OUTPUT) 288 Cw C2 C1
TRANSFER ATTRIBUTES (INPUT) A31-A0 (INPUT) 280 BADD3BADD2 (OUTPUT) TS (INPUT) RASx (OUTPUT) CAS3CAS0 (OUTPUT)
254
281
252
253
282
283
295
296
121 298 AMUX (OUTPUT) 297 WE (WRITE CYCLE OUTPUT)
122
123 298
293
294
TA (OUTPUT) 257 TBI (OUTPUT) TEA (INPUT)
258 259
300
301
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Figure 37. External TS68040 DRAM Burst Cycles Timing Diagram
C1 CLKO1 (OUTPUT) 288 TRANSFER ATTRIBUTES (INPUT) A31-A0 (INPUT) 280 BADD3BADD2 (OUTPUT) TS (INPUT) 252 253 299 299 Cw C2 C1 C2
282 RASx (OUTPUT) 296 CAS3CAS0 (OUTPUT) 295A 296
295
295
AMUX (OUTPUT) 297 WE (WRITE CYCLE OUTPUT)
293 258 258 257
TA (OUTPUT) TBI (OUTPUT)
257
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Figure 38. External TS68040 Parity Bit Checking Timing Diagram
D31-D0 (INPUT)
PRTY3PRTY0 (OUTPUT) 212 213
(a) Generation Timing Diagram
CPU Clears PERn Bit
C1 CLKO1 (OUTPUT) TRANSFER ATTRIBUTES (INPUT) A31-A0 (INPUT) BADD3BADD2 (OUTPUT) TS (INPUT) TA (OUTPUT)
C2
C1
302 D31-D0, (INPUT) 305 PRTY3PRTY0 (INPUT)
303
306
90 PERR (OUTPUT)
91
(b) Checking Timing Diagram
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IDMA AC Electrical Specifications
GND = 0 VDC, TC = -55 to +125C.The electrical specifications in this document are preliminary (See Figure 39 and Figure 40).
25.0 MHz Number 1 2 3(1) 4 5
(1) (1)
33.34 MHz Min 3 3 3tcyc + tAIST + tCLSA Max 18 18 Unit ns ns
Characteristic CLKO1 Low to DACK, DONE Asserted CLKO1 Low to DACK, DONE Negated DREQx Asserted to AS Asserted (for DMA Bus Cycle) Asynchronous Input Setup Time to CLKO1 Low Asynchronous Input Hold Time from CLKO1 Low AS to DACK Assertion Skew DACK to DONE Assertion Skew AS, DACK, DONE Width Asserted AS, DACK, DONE Width Asserted (Fast Termination Cycle) Asynchronous Input Setup Time to CLKO1 Low Asynchronous Input Hold Time from CLKO1 Low DREQ Input Setup Time to CLKO1 Low DREQ Input Hold Time from CLKO1 Low DONE Input Setup Time to CLKO1 Low DONE Input Hold Time From CLKO1 Low DREQ Asserted to AS Asserted
Min 3 3
Max 24 24
12 0 0 -8 70 28 5 10 20 5 20 5 2
20 8 -
9 0 0 -6 52.5 20.5 4 7.5 15 3.75 15 3.75 2
15 6 -
ns ns ns ns ns ns ns ns ns ns ns ns clk
6 7 8 8A 10(1) 11 12 13
(1) (2) (2)
14(2) 15(2) 16
(2)
Notes:
1. These specifications are for asynchronous mode. 2. These specifications are for synchronous mode.
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Figure 39. IDMA Signal Asynchronous Timing Diagram
CPU_CYCLE (IDMA REQUEST) S0 CLKO1 (OUTPUT) 4 DREQ (INPUT) AS (OUTPUT) 1 DACK (OUTPUT) 7 DONE (OUTPUT) 1 DONE (INPUT) 10 11 2 5 6 3 8 1 S1 S2 S3 S4 S5 S0 S1 S2 IDMA_CYCLE S3 S4 S5
Figure 40. IDMA Signal Synchronous Timing Diagram
CPU_CYCLE (IDMA REQUEST) S0 CLKO1 (OUTPUT) 12 DREQ (INPUT) AS (OUTPUT) 1 DACK (OUTPUT) 7 DONE (OUTPUT) 1 DONE (INPUT) 15 14 2 13 6 16 8 1 S1 S2 S3 S4 S5 S0 S1 IDMA_CYCLE S2 S3 S4 S5
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PIP/PIO Electrical Specifications
GND = 0 Vdc, TC = -55 to +125C.The electrical specifications in this document are preliminary (See Figure 41 to Figure 45).
25.0 MHz Number 21 22 23 24 25 26 27 28 29 30 Characteristic Data-In Setup Time to STBI Low Data-In Hold Time to STBI High STBI Pulse Width STBO Pulse Width Data-Out Setup Time to STBO Low Data-Out Hold Time from STBO High STBI Low to STBO Low (Rx Interlock) STBI Low to STBO High (Tx Interlock) Data-In Setup Time to Clock Low Data-In Hold Time from Clock Low Clock High to Data-Out Valid (CPU Writes Data, Control, or Direction) Note: Min 0 2.5 - t3 1.5 1 CLKO1 5 ns 2 5 2 20 10 Max 2 25 Min 0 2.5 - t3 1.5 1 CLKO1 5 ns 2 5 2 15 7.5 33.34 MHz Max 2 25 Unit ns clk clk clk clk clk clk ns ns ns
1. t3 = spec. 3 on "AC Electrical Specifications Control Timing" on page 17.
Figure 41. PIP Rx (Interlock Mode)
25 26
DATA OUT
STRBO (OUTPUT)
28 23 STRBI (INPUT)
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Figure 42. PIP Tx (Interlock Mode)
21 22
DATA IN
23 STRBI (INPUT)
24 STRBO (OUTPUT)
Figure 43. PIP Tx (Pulse Mode)
21 22
DATA IN
23 STBI (INPUT)
24 STBO (OUTPUT)
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Figure 44. PIP Tx (Pulse Mode)
25 26
DATA OUT
24 STBO (OUTPUT)
23 STBI (INPUT)
Figure 45. Parallel I/O Data-in/Data-out Timing Diagram
CLKO1 (OUTPUT)
DATA IN 29
30
DATA OUT
31
CPU WRITE S4
Interrupt Controller AC Electrical Specifications
GND = 0 Vdc, TC = -55 to +125C.The electrical specifications in this document are preliminary. (See Figure 46 and Figure 47).
25.0 MHz Number 35 36 37 38 Characteristic Port C Interrupt Pulse Width Low (Edge Triggered Mode) Minimum Time Between Active Edges Port C Clock High to IOUT Valid (Slave Mode) Clock High to RQOUT Valid (Slave Mode) Min 70 70 Max 20 20 33.34 MHz Min 55 55 Max 17 17 Unit ns clk ns ns
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Figure 46. Interrupts Timing Diagram
Port C (INPUT)
35 36
Figure 47. Slave Mode: Interrupts Timing Diagram
CLKO1 (OUTPUT)
IOUT2IOUT0 (OUTPUT) 37
RQOUT (OUTPUT) 38
BAUD Rate Generator AC Electrical Specifications GND = 0 VDC, TC = -55 to +125C.The electrical specifications in this document are preliminary (See Figure 48).
25.0 MHz Number 50 51 52 Characteristic BRGO Rise and Fall Time BRGO Duty Cycle BRGO Cycle Min 40 40 Max 10 60 33.34 MHz Min 40 30 Max 7.5 60 Unit ns % ns
Figure 48. Baud Rate Generator Output Signals
50 50
BRGOx
51 52
51
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Timer Electrical Specifications
GND = 0 VDC, TC = -55 to +125C. The electrical specifications in this document are preliminary (See Figure 49).
25.0 MHz Number 61 62 63 64 65 Characteristic TIN/TGATE Rise and Fall Time TIN/TGATE Low Time TIN/TGATE High Time TIN/TGATE Cycle Time CLKO1 High to TOUT Valid Symbol trf tTO Min 10 1 2 3 3 Max 25 33.34 MHz Min 10 1 2 3 3 Max 22 Unit ns clk clk clk ns
Figure 49. CPM General-purpose Timers
60
CLKO1 (OUTPUT) 61 62 TIN/TGATE (INPUT) 63
64 61 65 TOUT (OUTPUT)
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SI Electrical Specifications
GND = 0 VDC, TC = -55 to +125C.The electrical specifications in this document are preliminary (See Figure 50 to Figure 54).
25.0 MHz Number 70(1)(3) 71
(1) (2)
33.34 MHz Min P+10 P+10 20 35 42 35 10 10 10 10 10 0 P+10 P+10 1 42 42 Max 10 15 15 45 45 45 65 65 42 16 30 0 Unit MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns MHz ns ns ns L1TCLK ns ns ns
Characteristic L1RCLK, L1TCLK Frequency (DCS = 0) L1RCLK, L1TCLK Width Low (DCS = 0) L1RCLK, L1TCLK Width High (DCS = 0) L1TXD, L1ST(1-4), L1RQ, L1CLKO Rise/Fall Time L1RSYNC, L1TSYNC Valid to L1CLK Edge (SYNC Setup Time) L1CLK Edge to L1RSYNC, L1TSYNC Invalid (SYNC Hold Time) L1RSYNC, L1TSYNC Rise/Fall Time L1RXD Valid to L1CLK Edge (L1RXD Setup Time) L1CLK Edge to L1RXD Invalid (L1RXD Hold Time) L1CLK Edge to L1ST(1-4) Valid L1SYNC Valid to L1ST(1-4) Valid L1CLK Edge to L1ST(1-4) Invalid L1CLK Edge to L1TXD Valid L1TSYNC Valid to L1TXD Valid L1CLK Edge to L1TXD High Impedance L1RCLK, L1TCLK Frequency (DSC = 1) L1RCLK, L1TCLK Width Low (DSC = 1) L1RCLK, L1TCLK Width High (DSC = 1) L1CLK Edge to L1CLKO Valid (DSC = 1) L1RQ Valid Before Falling Edge of L1TSYNC L1GR Setup Time L1RG Hold Time L1CLK Edge to L1SYNC Valid (FSD = 00, CNT = 0000, BYT = 0, DSC = 0)
Min P+10 P+10 20 35 42 35 10 10 10 10 10 0 P+10 P+10 1 42 42 -
Max 10 15 15 45 45 45 65 65 42 12.5 30 0
71A
72 73 74 75 76 77 78 78A
(4)
79 80 80A
(4)
81 82 83 83A
(2)
84 85(3) 86 87
(3) (3)
88 Notes: 1. 2. 3. 4.
The ratio SyncCLK/L1RC LK must be greater than 2.5/1. Where P = 1/CLKO1. Thus for a 25 MHz CLKO1 rate, P = 40 ns. These specs are valid for IDL mode only. The strobes and Txd on the first bit of the frame become valid after L1CLK edge or L1SYNC, whichever is later.
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Figure 50. SI Receive Timing with Normal Clocking (DSC = 0)
L1RCLK (FE = 0,CE = 0) (INPUT) 72 70 L1RCLK (FE =1,CE = 1) (INPUT) 71 75 RFCD = 1 L1RSYNC (INPUT) 73 74 76 L1RXD (INPUT) BIT0 77
78 L1ST (4-1) (OUTPUT)
79
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Figure 51. SI Receive Timing with Double Speed Clocking (DSC = 1)
72 L1RCLK (FE = 0, CE = 0) (INPUT) 83A
82
L1RCLK (FE = 1, CE = 1) (INPUT) 75 RFCD = 1 L1RSYNC (INPUT) 73 74 76 L1RXD (INPUT) BIT0 77
78 L1ST (4-1) (OUTPUT)
79
L1CLKO (OUTPUT) 84
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Figure 52. SI Transmit Timing with Normal Clocking (DSC = 0)
L1TCLK (FE = 0, CE = 0) (INPUT)
72 70
L1TCLK (FE = 1, CE = 1) (INPUT) 75 L1TSYNC (OUTPUT) 73 74 80A L1TXD (INPUT) 80 78A L1ST (4-1) (OUTPUT) 78 BIT0
71
TFCD = 0 81
79
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Figure 53. SI Transmit Timing with Double Speed Clocking (DSC = 1)
72 L1RCLK (FE = 0, CE = 0) (INPUT) 82 L1RCLK (FE = 1, CE = 1) (INPUT) 75 L1TSYNC (INPUT) 73 74 TFCD = 0 80A L1TXD (OUTPUT) 80 78A L1ST (1-4) (OUTPUT) 78 79 BIT0 81 83A
L1CLKO (OUTPUT) 84
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Figure 54. IDL Timing SI Transmit Timing with Double Speed Clocking (DSC = 1)
SCC in NMSI Mode-external Clock Electrical Specifications
GND = 0 VDC, TC = -55 to +125C. The electrical specifications in this document are preliminary (See Figure 55 to Figure 57).
25.0 MHz Number 100
(1)
33.34 MHz Min CLKO1 CLKO1 + 5 ns 0 0 40 40 0 40 Max 15 50 50 ns ns ns ns ns ns ns Unit
Characteristic RCLK1 and TCLK1 Width High RCLK1 and TCLK1 Width Low RCLK1 and TCLK1 Rise/Fall Time TXD1 Active Delay (From TCLK1 Falling Edge) RTS1 Active/Inactive Delay (From TCLK1 Falling Edge) CTS1 Setup Time to TCLK1 Rising Edge RXD1 Setup Time to RCLK1 Rising Edge RXD1 Hold Time from RCLK1 Rising Edge CD1 Setup Time to RCLK1 Rising Edge
Min CLKO1 CLKO1 + 5 ns 0 0 40 40 0 40
Max 15 50 50 -
101 102 103 104 105 106 107
(2)
108 Notes:
1. The ratio SyncCLK/RCLK1 and SyncCLK/TCLK1 must be greater or equal to 2.25/1. 2. Also applies to CD and CTS hold time when they are used as external sync signals.
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SCC in NMSI Mode-internal Clock Electrical Specifications
GND = 0 Vdc, TC = -55 to +125C. The electrical specifications in this document are preliminary (See Figure 55 to Figure 57).
25.0 MHz Number 100(1) 102 103 104 105 106 107
(2)
33.34 MHz Min 0 0 40 40 0 40 0 Max 11 30 30 Unit MHz ns ns ns ns ns ns ns
Characteristic RCLK1 and TCLK1 Frequency RCLK1 and TCLK1 Rise/Fall Time TXD1 Active Delay (From TCLK1 Falling Edge) RTS1 Active/Inactive Delay (From TCLK1 Falling Edge) CTS1 Setup Time to TCLK1 Rising Edge RXD1 Setup Time to RCLK1 Rising Edge RXD1 Hold Time from RCLK1 Rising Edge CD1 Setup Time to RCLK1 Rising Edge
Min 0 0 0 40 40 0 40
Max 8.3 30 30 -
108 Notes:
1. The ratio SyncCLK/RCLK1 and SyncCLK/TCLK1 must be greater or equal to 3/1. 2. Also applies to CD and CTS hold time when they are used as external sync signals.
Figure 55. SCC NMSI Receive
102 RCLK1 100 106 RXD1 (INPUT) 107 CD1 (INPUT) 108 102 101
107 CD1 (SYNCINPUT)
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Figure 56. SCC NMSI Transmit
102 TCLK1 100 103 TXD1 (OUTPUT) 102 101
RTS1 (OUTPUT) 104 105 CTS1 (INPUT) 104
107 CTS1 (SYNCINPUT)
Figure 57. HDLC BUS Timing
102 102 101 TCLK1 100 103 TXD1 (OUTPUT)
RTS1 (OUTPUT)
104 107 105
104
CTS1 (ECHO INPUT)
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Ethernet Electrical Specifications
GND = 0 Vdc, TC = -55 to +125C. The electrical specifications in this document are preliminary (See Figure 58 to Figure 63).
25.0 MHz Number 120 121 122 123(1) 124 125 126 127 128 129 130(1) 131 132 133 134 135 136 137 138(2) 139(2) Notes: Characteristic CLSN Width High RCLK1 Rise/Fall Time RCLK1 Width Low RCLK1 Width High RXD1 Setup Time RXD1 Hold Time RENA Active Delay (from RCLK1 rising edge of the last data bit) RENA Width Low TCLK1 Rise/Fall Time TCLK1 Width Low TCLK1 Width High TXD1 Active Delay (from TCLK1 rising edge) TXD1 Inactive Delay (from TCLK1 rising edge) TENA Active Delay (from TCLK1 rising edge) TENA Inactive Delay (from TCLK1 rising edge) RSTRT Active Delay (from TCLK1 falling edge) RSTRT Inactive Delay (from TCLK1 falling edge) RRJCT Width Low CLKO1 Low to SDACK Asserted CLKO1 Low to SDACK Negated Min 40 CLKO1 + 5 ns CLKO1 20 5 10 100 CLKO1 + 5 ns CLKO1 10 10 10 10 10 10 1 Max 15 15 50 50 50 50 50 50 20 20 33.34 MHz Min 40 CLKO1 + 5 ns CLKO1 20 5 10 100 CLKO1 + 5 ns CLKO1 10 10 10 10 10 10 1 Max 15 15 50 50 50 50 50 50 20 20 ns ns ns ns ns ns CLKO1 ns ns ns ns ns ns ns Unit ns ns
1. SyncCLK/RCLK1 and SyncCLK/TCLK1 must be greater or equal to 2.25/1 2. SDACK is asserted whenever the SDMA writes the incoming frame DA into memory.
Figure 58. Ethernet Collision Timing
CLSN (CTS1) (INPUT) 120
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Figure 59. Ethernet Receive Timing
121 121 122 RCLK1 123 124 RXD1 (INPUT) 125 127 RENA (CD1) (INPUT) 126 LAST BIT
Figure 60. Ethernet Transmit Timing
128 128 129 TCLK1 (NOTE 1) 130 131 TXD1 (OUTPUT) 132
133 TENA (RTS1) (OUTPUT) 134
RENA (CD1) (INPUT) (NOTE 2)
Notes:
1. Transmit clock invert (TCI) bit in GSMR is set. 2. If RENA is deasserted before TENA, or RENA is not asserted at all during transit, then CSL bit is set in the buffer descriptor at the end of frame transmission.
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Figure 61. CAM Interface Receive Start Timing
RCLK1
RXD1 (INPUT)
0
1
1
Bit # 1
Bit # 2
START FRAME DELIMITER
135 RSTRT (OUTPUT)
136
Note:
Valid for the ethernet protocol only.
Figure 62. CAM Interface Reject Timing
137 RRJCT (INPUT)
Note:
Valid for the ethernet protocol only.
Figure 63. SDACK Timing Diagram
SDMA CYCLE S0 CLKO1 (OUTPUT) AS (OUTPUT) SDACKx (OUTPUT) 138
139
S1
S2
S3
S4
S5
Note:
SDACKx is asserted when the SDMA writes the received Ethernet frame into memory.
SMC Transparent Mode Electrical Specifications
GND = 0 VDC, TC = -55 to +125C. The electrical specifications in this document are preliminary (See Figure 64).
25.0 MHz Number 150(1) 151 151A Characteristic SMCLK Clock Period SMCLK Width Low SMCLK Width High Min 100 50 50 Max 33.34 MHz Min 100 50 50 Max Unit ns ns ns
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SMC Transparent Mode Electrical Specifications
GND = 0 VDC, TC = -55 to +125C. The electrical specifications in this document are preliminary (See Figure 64).
25.0 MHz Number 152 153 154 155 Note: Characteristic SMCLK Rise/Fall Time SMTXD Active Delay (from SMCLK falling edge) SMRXD/SYNC1 Setup Time SMRXD/SYNC1 Hold Time Min 10 20 5 Max 15 50 33.34 MHz Min 10 20 5 Max 15 50 Unit ns ns ns ns
1. The ratio SyncCLK/SMCLK must be greater or equal to 2/1. SMC Transparent.
Figure 64. SMC Transparent
152 152 151 151A
SMCLK
150
TXD1 (OUTPUT)
Note 1
153 154 155
SYNC1
154
RXD1 (INPUT)
155
Note:
This delay is equal to an integer number of "Character length" clocks.
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SPI Master Electrical Specifications
GND = 0 Vdc, TC = -55 to +125C. The electrical specifications in this document are preliminary (See Figure 65 and Figure 66).
25.0 MHz Number 160 161 162 163 164 165 166 167 Characteristic Master Cycle Time Master Clock (SPICLK) High or Low Time Master Data Setup Time (Inputs) Master Data Hold Time (Inputs) Master Data Valid (after SPICLK Edge) Master Data Hold Time (Outputs) Rise Time: Output Fall Time: Output Min 4 2 50 0 0 Max 1024 512 20 15 15 33.34 MHz Min 4 2 50 0 0 Max 1024 512 20 15 15 Unit tcyc tcyc ns ns ns ns ns ns
Figure 65. SPI Master (CP = 0)
167 166 SPICLK CI=0 OUTPUT 161 SPICLK CI=1 OUTPUT 162 163 SPIMISO INPUT MSB IN 165 SPIMOSI OUTPUT "1" MSB OUT 167 DATA DATA LSB IN 164 LSB OUT "1" 166 MSB OUT MSB IN 161 167 160
166
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Figure 66. SPI Master (CP = 1)
160 SPICLK CI=0 OUTPUT 161 SPICLK CI=1 OUTPUT 161 SPIMISO INPUT 160 163 167 166
166 162
MSB IN
DATA 165
LSB IN 164 LSB OUT "1" 166
MSB
SPIMOSI OUTPUT
"1"
MSB OUT 167
DATA
MSB
SPI Slave Electrical Specifications
GND = 0 Vdc, TC = -55 to +125C. The electrical specifications in this document are preliminary (See Figure 67 and Figure 68).
25.0 MHz Number 170 171 172 173 174 175 176 177 178 179 180 181 182 Characteristic Slave Cycle Time Slave Enable Lead Time Slave Enable Lag Time Slave Clock (SPICLK) High or Low Time Slave Sequential Transfer Delay (Does Not Require Deselect) Slave Data Setup Time (Inputs) Slave Data Hold Time (Inputs) Slave Access Time Slave SPIMISO Disable Time Slave Data Valid (after SPICLK Edge) Slave Data Hold Time (Outputs) Rise Time: Input Fall Time: Input 0 Min 2 15 15 1 1 20 20 50 50 50 15 15 0 Max 33.34 MHz Min 2 15 15 1 1 20 20 50 50 50 15 15 Max Unit tcyc ns ns tcyc tcyc ns ns ns ns ns ns ns ns
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Figure 67. SPI Slave (CP = 0)
172 SPISEL INPUT 182 181 SPICLK CI=0 INPUT 173 SPICLK CI=1 INPUT 173 177 SPIMISO OUTPUT 175 SPIMOSI INPUT MSB IN DATA LSB IN MSB IN MSB OUT 176 180 DATA 170 174 171
181 182 179 LSB OUT 181 180 UNDEF. 182 178 MSB OUT
Figure 68. SPI Slave (CP = 1)
SPISEL INPUT 170 173 SPICLK CI=0 INPUT 171 SPICLK CI=1 INPUT 179 177 SPIMISO OUTPUT UNDEF. MSB OUT 176 175 SPIMOSI INPUT MSB IN DATA LSB IN DATA 179 182 180 SLAVE LSB OUT 181 178 UNDEF. 173 172 181 182 174
181
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JTAG Electrical Specifications
GND = 0 Vdc, TC = -55 to +125C. The electrical specifications in this document are preliminary (See Figure 69 and Figure 72).
25.0 MHz Number Characteristic TCK Frequency of Operation 1 2 3 6 7 8 9 10 11 12 13 14 15 TCK Cycle Time in Crystal Mode TCK Clock Pulse Width Measured at 1.5V TCK rise and Fall Times Boundary Scan Input Data Setup Time Boundary Scan Input Data Hold Time TCK Low to Output Data Valid TCK Low to Output High Impedance TMS, TDI Data Setup Time TMS, TDI Data Hold Time TCK Low to TDO Data Valid TCK Low to TDO High Impedance TRST Assert Time TRST Setup Time to TCK Low Min 0 40 18 0 10 18 0 0 10 10 0 0 100 40 Max 25 3 30 40 20 20 33.34 MHz Min 0 40 18 0 10 18 0 0 10 10 0 0 100 40 Max 25 3 30 40 20 20 Unit MHz ns ns ns ns ns ns ns ns ns ns ns ns ns
Figure 69. Test Clock Input Timing Diagram
1 2 VIH VM VIL 3 3 VM 2
TCK (INPUT)
Figure 70. TRST Timing Diagram
TCK (INPUT)
15 TRST (INPUT) 14
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Figure 71. Boundary Scan (JTAG) Timing Diagram
TCK (INPUT) VIH VIL 6 DATA INPUTS 8 7
INPUT DATA VALID
DATA OUTPUTS 9 DATA OUTPUTS 8 DATA OUTPUTS
OUTPUT DATA VALID
OUTPUT DATA VALID
Figure 72. Test Access Port Timing Diagram
TCK (INPUT) VIH VIL 10 TDI TMS (INPUT) 12 TDO (OUTPUT) 13 TDO (OUTPUT) 12 TDO (OUTPUT) OUTPUT DATA VALID 11
INPUT DATA VALID
OUTPUT DATA VALID
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Functional Description
CPU32+ Core
The CPU32+ core is a CPU32 that has been modified to connect directly to the 32-bit IMB and apply the larger bus width. Although the original CPU32 core had a 32-bit internal data path and 32-bit arithmetic hardware, its interface to the IMB was 16 bits. The CPU32+ core can operate on 32-bit external operands with one bus cycle. This allows the CPU32+ core to fetch a long-word instruction in one bus cycle an to fetch two wordlength instructions in one bus cycle, filling the internal instruction queue more quickly. The CPU32+ core can also read and write 32-bits of data in one bus cycle. Although the CPU32+ instruction timings are improved, its instruction set is identical to that of the CPU32. It will also execute the entire 68000 instruction set. It contains the same background debug mode (BDM) features as the CPU32. No new compilers, assemblers or other software support tools need be implemented for the CPU32+; standard CPU32 tools can be used. The CPU32+ delivers approximately 4.5 MIPS at 25 MHz, based on the standard (accepted) assumption that a 10-MHz 68000 delivers 1 VAX MIPS. If an application requires more performance, the CPU32+ can be disabled, allowing the rest of the QUICC to operate as an intelligent peripheral to a faster processor. The QUICC provides a special mode called TS68040 companion mode to allow it to conveniently interface to members of the TS68040 family. This two-chip solution provides a 22-MIPS performance at 25 MHz. The CPU32+ also offers automatic byte alignment features that are not offered on the CPU32. These features allow 16- or 32-bit data to be read or written at an odd address. The CPU32+ automatically performs the number of bus cycles required.
System Integration Module (SIM60)
The SIM60 integrates general-purpose features that would be useful in almost any 32bit processor system. The term "SIM60" is derived from the QUICC part number, TS68EN360. The SIM60 is an enhanced version of the SIM40 that exists on the TS68332 device. First, new features, such as a DRAM controller and breakpoint logic, have been added. Second, the SIM40 was modified to support a 32-bit IMB as well as a 32-bit external system bus. Third, new configurations, such as slave mode and internal accesses by an external master, are supported. Although the QUICC is always a 32-bit device internally, it may be configured to operate with a 16-bit data bus. Regardless of the choice of the system bus size, dynamic bus sizing is supported. Bus sizing allows 8-16-, and 32-bit peripherals and memory to exist in the 32-bit system bus mode and 8- and 16-bit peripherals and memory to exist in the 16-bit system bus mode.
Communications The CPM contains features that allow the QUICC to excel in communications and conProcessor Module (CPM) trol applications. These features may be divided into three sub-groups:
* * * Communications Processor (CP) Two IDMA Controllers Four General-purpose Timers
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The CP provides the communication features of the QUICC. Included are a RISC processor, four SCCs, two SMCs, one SPI, 2.5K bytes of dual-port RAM, an interrupt controller, a time slot assigner, three parallel ports, a parallel interface port, four independent baud rate generators, and fourteen serial DMA channels to support the SCCs, SMCs, and SPI. The IDMAs provide two channels of general-purpose DMA capability. They offer highspeed transfers, 32-bit data movement, buffer chaining, and independent request and acknowledge logic. The RISC controller may access the IDMA registers directly in the buffer chaining modes. The QUICC IDMAs are similar to, yet enhancements of, the one IDMA channel found on the TS68302. The four general-purpose timers on the QUICC are functionally similar to the two general-purpose timers found on the TS68302. However, they offer some minor enhancements, such as the internal cascading of two timers to form a 32-bit timer. The QUICC also contains a periodic interval timer in the SIM60, bringing the total to five on-chip timers.
Ethernet on QUICC
The Ethernet protocol is available only on the Ethernet version of the QUICC called the TS68EN360. The non-Ethernet version of the QUICC is the MC68360. The term "QUICC" is the overall device name that denotes all versions of the device. The TS68EN360 is a superset of the MC68360, having the additional option allowing Ethernet operation on any of the four SCCs. Due to performance reason not ass SCCs can be configured as Ethernet controller at the same time. The TS68EN360 is not restricted only to Ethernet operation. HDLC, UART, and other protocols may be used to allow dynamic switching between protocols. See Appendix A Serial Performance for available SCC performance. When the MODE bits of the SCC GSMR select the Ethernet protocol, then that SCC performs the full set of IEEE 802.3/Ethernet CSMA/CD media access control and channel interface functions (see Figure 73).
Figure 73. Ethernet Block Diagram
IMB
CONTROL REGISTERS
RANDOM NO.
SLOT TIME AND DEFER COUNTER
PERIPHERAL BUS
CLOCK GENERATOR
RX CLOCK TX CLOCK
INTERNAL CLOCKS RRJCT RSTRT CD = RENA CTS = CLSN RTS = TENA RECEIVER CONTROL UNIT RECEIVE DATA FIFO TRANSMIT DATA FIFO TRANSMITTER CONTROL UNIT CD = RENA CTS = CLSN
RXD
SHIFTER
SHIFTER
TXD
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Upgrading Designs from the TS68302
Since the QUICC is a next-generation TS68302, many designers currently using the TS68302 may wish to use the QUICC in a follow-on design. The following paragraphs briefly discuss this endeavor in terms of architectural approach, hardware issues, and software issues. The QUICC is the logical extension of the TS86302, but the overall architecture and philosophy of the TS86302 design remains intact in the QUICC. The QUICC keeps the best features of the TS86302, while making the changes required to provide for the increased flexibility, integration, and performance requested by customers. Because the CPM is probably the most difficult module to learn, anyone who has used the TS86302 can easily become familiar with the QUICC since the CPM architectural approach remains intact. The most significant architectural change made on the QUICC was the translation of the design into the standard 68300 family IMB architecture, resulting in a faster CPU and different system integration features. Although the features of the SIM60 do not exactly correspond to those of the TS86302 SIM, they are very similar. Because of the similarity of the QUICC SIM60 and CPU to other members of the 68300 family, such as the TS68332, previous users of these devices will be comfortable with these same features on the QUICC. Hardware Compatibility Issues The following list summarizes the hardware differences between the TS86302 and the QUICC: * * Pinout - The pinout is not the same. The QUICC has 240 pins; the TS86302 has 132 pins. Package - Both devices offer PGA and PQFP packages. However, the QUICC QFP package has a 20-mil pitch; whereas, the TS86302 QFP package has a 25-mil pitch. System Bus - The system bus signals now look like those of the TS68020 as opposed to those of the 68000. It is still possible to interface 68000 peripherals to the QUICC, utilizing the same techniques used to interface them to a TS68020. System Bus in Slave Mode - A number of QUICC pins take on new functionality in slave mode to support an external TS68EC040. On the TS68302, the pin names generally remained the same in slave mode. Peripheral Timing - The external timings of the peripherals (SCCs, timers, etc.) are very similar (if not identical) to corresponding peripherals on the TS68302. Pin Assignments - The assignment of peripheral functions to I/O pins is different in several ways. First, the QUICC contains more general-purpose parallel I/O pins than the TS68302. However, the QUICC offers many more functions than even a 240-pin package would normally allow, resulting in more multifunctional pins than the TS68302.
Architectural Approach
*
*
* *
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Software Compatibility Issues
The following list summarizes the major software differences between the TS68302 and the QUICC: * Since the CPU32+ is a superset of the 68000 instruction set, all previously written code will run. However, if such code is accessing the TS68302 peripherals, it will require some modification. The QUICC contains an 8-Kbyte block of memory as opposed to a 4-Kbyte block on the TS68302. The register addresses within that memory map are different. The code used to initialize the system integration features of the TS68302 has to be modified to write the corresponding features on the QUICC SIM60. As much as possible, QUICC CPM features were made identical to those of the TS68302 CP. The most important benefit is that the code flow (if not the code itself) will port easily from the TS68302 to the QUICC. The nuances learned from the TS68302 will still be useful in the QUICC. Although the registers used to initialize the QUICC CPM are new (for example, the SCM on the TS68302 is replaced with the GSMR and PSMR on the QUICC), most registers retain their original purpose such as the SCC event, SCC mask, SCC status, and command registers. The parameter RAM of the SCCs is very similar, and most parameter RAM register names and usage are retained. More importantly, the basic structure of a buffer descriptor (BD) on the QUICC is identical to that of the TS68302, except for a few new bit functions that were added. (In a few cases, a bit in a BD status word had to be shifted.) When porting code from the TS68302 CP to the QUICC CPM, the software writer may find that the QUICC has new options to simplify what used to be a more codeintensive process. For specific examples, see the INIT TX AND RX PARAMETERS, GRACEFUL STOP TRANSMIT, and CLOSE BD commands.
* * *
*
*
Preparation for Delivery
Packaging Microcircuits are prepared for delivery in accordance with MIL-PRF-38535 or Atmel standards. Atmel offers a certificate of compliances with each shipment of parts, affirming the products are in compliance either with MIL-STD-883 or Atmel standard and guarantying the parameters not tested at temperature extremes for the entire temperature range. MOS devices must be handled with certain precautions to avoid damage due to accumulation of static charge. Input protection devices have been designed in the chip to minimize the effect of this static buildup. However, the following handling practices are recommended: a) Devices should be handled on benches with conductive and grounded surfaces. b) Ground test equipment, tools and operator. c) Do not handle devices by the leads. d) Store devices in conductive foam or carriers. e) Avoid use of plastic, rubber, or silk in MOS areas. f) Maintain relative humidity above 50% if practical.
Certificate of Compliance
Handling
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Package Mechanical Data
241-pin - PGA
Inches Dim A C Min 1.840 0.110 0.016 0.045 0.045 Max 1.880 0.140 0.020 0.055 0.055
Millimeters Min 46.74 2.79 0.41 1.143 1.143 Max 47.75 3.56 0.51 1.4 1.4
(top view)
A
D E F G K
0.100 BASIC 0.150 0.170
2.54 BASIC 3.81 4.32
C G E
T
G
A1
(BOTTOM VIEW)
A
A K
F
1
18
D
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240-pin - CERQUAD
S U
180 181 121 120
VIEW AC
4 PLACES
VIEW AC AD AD G -X- J D 0.08(0.003) M T L-N
S
Y
X = L, M or N SECTION AD
240 PLACES
V
B
F
-N-
-L-
Z
P
240 61
M
S
1
60
-M- A
4 x 60 TIPS
MILLIMETERS DIM MIN 30.86 30.86 3.67 0.18 3.10 0.17 MAX 31.75 31.75 4.15 0.30 3.90 0.23
INCHES MIN 1.215 1.215 0.144 0.007 0.122 0.007 MAX 1.250 1.250 0.163 0.012 0.154 0.009
0.25(0.010) T L-N M
W C E
0.20 (0.008) M H L-N
S
M
S
A B
-H-
DATUM PLANE
C D E F G J
0.10(0.004) AB VIEW AE VIEW AE -T-
SEATING PLANE
0.50 BSC 0.13 0.45 0.175 0.55
0.019 BSC 0.005 0.018 0.007 0.021
2 -H-
DATUM PLANE
K P R
0.25 BSC 0.15 BSC 34.41 34.75
0.010 BSC 0.006 BSC 1.355 1.37
K AA
S U V W Y Z AA AB 2
17.30 BSC 34.41 0.25 34.75 0.75
0.681 BSC 1.355 0.01 1.37 0.03
Notes:
1. Dimensioning and tolerancing per ASME Y 14.5, 1994. 2. Controlling dimension: millimeter. 3. Datum plane -H- is located at bottom of lead and is coincident with the lead where the lead exits the ceramic body at the bottom of the parting line. 4. Datums -L-, -M- and -N- to be determined at datum plane -H-. 5. Dimensions S and V to be determined at seating plane -T-. 6. Dimensions A and B define maximum ceramic body dimensions including glass protrusion and top and bottom mismatch.
17.30 BSC 0.12 0.13
0.681 BSC 0.005 0.005
1.80 REF 0.95 REF 1 7
0.071 REF 0.037 REF 1 7
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Ordering Information
Hi-REL Product
Commercial Atmel Part-Number TS68EN360MRB/C25L TS68EN360MRB/C33L TS68EN360MR1B/C25L TS68EN360MR1B/C33L TS68EN360MAB/C25L TS68EN360MAB/C33L TS68EN360DES01MXCL TS68EN360DES02MXCL TS68EN360DES01MXAL TS68EN360DES02MXAL TS68EN360DES01MYAL TS68EN360DES02MYAL Norms MIL-STD-883 MIL-STD-883 MIL-STD-883 MIL-STD-883 MIL-STD-883 MIL-STD-883 DSCC DSCC DSCC DSCC DSCC DSCC Package PGA 241 Gold PGA 241 Gold PGA 241 Tinned PGA 241 Tinned CERQUAD 240 CERQUAD 240 PGA 241 Gold PGA 241 Gold PGA 241 Tinned PGA 241 Tinned CERQUAD 240 CERQUAD 240 Temperature Range Tc (C) -55/+125 -55/+125 -55/+125 -55/+125 -55/+125 -55/+125 -55/+125 -55/+125 -55/+125 -55/+125 -55/+125 -55/+125 Frequency (MHz) 25 33 25 33 25 33 25 33 25 33 25 33 Drawing Number 5962-9760701MXC 5962-9760702MXC 5962-9760701MXA 5962-9760702MXA 5962-9760701MYA 5962-9760702MYA
Standard Product
Commercial Atmel Part-Number TS68EN360VR25L TS68EN360MR25L TS68EN360VA25L TS68EN360MA25L TS68EN360VR33L TS68EN360MR33L TS68EN360VA33L TS68EN360MA33L Norms Atmel Standard Atmel Standard Atmel Standard Atmel Standard Atmel Standard Atmel Standard Atmel Standard Atmel Standard Package PGA 241 PGA 241 CERQUAD 240 CERQUAD 240 PGA 241 PGA 241 CERQUAD 240 CERQUAD 240 Temperature Range Tc (C) -40/+85 -55/+125 -40/+85 -55/+125 -40/+85 -55/+125 -40/+85 -55/+125 Frequency (MHz) 25 25 25 25 33 33 33 33 Drawing Number Internal Internal Internal Internal Internal Internal Internal Internal
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(TSX) TS68EN360
M
R
1
B/C
25
X
Prototype version Generic Temperature range : (TC ) M : -55C, +125C V : -40C, +110C C : 0C, +70C Operating frequency : Package : R = Pin grid array 241 (gold) A = CERQUAD 240 (tin) Screening : Hirel lead finish : ___ = Standard _= _= 1= Gold (for PGA) Hot solder dip (for CERQUAD) Hot solder dip (for PGA - On request) B/C = MIL STD 883 Class B B/T = According to MIL-STD883 D/T = Standard + Burn in 25 : 25 MHz 33 : 33 MHz Revision level L:
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(c) Atmel Corporation 2002. Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company's standard warranty which is detailed in Atmel's Terms and Conditions located on the Company's web site. The Company assumes no responsibility for any errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice, and does not make any commitment to update the information contained herein. No licenses to patents or other intellectual property of Atmel are granted by the Company in connection with the sale of Atmel products, expressly or by implication. Atmel's products are not authorized for use as critical components in life support devices or systems. ATMEL (R) is the registered trademarks of Atmel. Other terms and product names may be the trademarks of others.
2113A-HIREL-03/02
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